EA-OEM-315 Embedded Artists, EA-OEM-315 Datasheet - Page 36

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EA-OEM-315

Manufacturer Part Number
EA-OEM-315
Description
KIT LPC3141 SODIMM 66X48 200POS
Manufacturer
Embedded Artists
Type
MCUr
Datasheet

Specifications of EA-OEM-315

Contents
Board
For Use With/related Products
LPC3141
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.29 Timer module
6.30 Pulse Width Modulation (PWM) module
6.31 System control registers
6.32 I
The LPC3141/3143 contains four fully independent timer modules, which can be used to
generate interrupts after a pre-set time interval has elapsed.
This module has the following features:
This PWM can be used to generate a pulse width modulated or a pulse density modulated
signal. With an external low pass filter, the module can be used to generate a low frequent
analog signal. A typical use of the output of the module is to control the backlight of an
LCD display.
This module has the following features:
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
The I
2
2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage
S
(SUP4) can be different from the LCD supply voltage (SUP8).
Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler
allows using either the module clock directly or the clock divided by 16 or 256.
Two modes of operation:
– Free-running timer: The timer generates an interrupt when the counter reaches
– Periodic timer: The timer generates an interrupt when the counter reaches zero. It
At any time the current timer value can be read.
At any time the value in the load register may be re-written, causing the timer to
restart.
Supports Pulse Width Modulation (PWM) with software controlled duty cycle.
Supports Pulse Density Modulation (PDM) with software controlled pulse density.
Audio interface compatible with the I
I
I
Supports LSB justified words of 16, 18, 20 and 24 bit.
Supports a configurable number of bit clock periods per word select period (up to 128
bit clock periods).
2
2
2
S receive block supports master mode and slave mode.
S transmit block supports master mode.
S receive/I
zero. The timer wraps around to 0xFFFF FFFF and continues counting down.
reloads the value from a load register and continues counting down from that
value. An interrupt will be generated every time the counter reaches zero. This
effectively gives a repeated interrupt at a regular interval.
All information provided in this document is subject to legal disclaimers.
2
S transmit modules have the following features:
Rev. 0.16 — 27 May 2010
2
S standard.
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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