ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 12

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ATSAM3S-EK

Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Datasheets

Specifications of ATSAM3S-EK

Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
4.3.4
4.3.5
4-4
Reset Circuitry
Power Supply and Management
The SAM3S chip internally generates the following clocks:
On-board NRST button BP1 provides an external reset control of the SAM3S.
The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor
of about 100 kOhm to VDDIO.
On the SAM3S-EK board, the NRST signal is connected to the LCD module and JTAG port.
Note:
The SAM3S-EK board is supplied with an external 5V DC block through input J9. It is protected by a
PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect
power supply connection.
The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V compo-
nents on the board.
Figure 4-4.
The SAM3S4/2/1 product series has different types of power supply pins:
SLCK, the Slow Clock, which is the only permanent clock of the system
MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz
Fast RC Oscillator
PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
VDDIN pin:
Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies.
The voltage ranges from 1.8V to 3.6V.
At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be
sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom
application, you need to check for these devices' datasheets about reset duration requirements. Then, you
need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the
RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subse-
quently activated by a software reset or a user reset. Refer to the SAM3S datasheet for in depth
information.
Power Block
J9
J9
MP179P 2.1mm
MP179P 2.1mm
+5V
1
2
2
1
1
MN12
MN12
MIC29152W U
MIC29152W U
Micrel's 1.5A LDO, TO263-5
Micrel's 1.5A LDO, TO263-5
VIN
SD
MN9
MN9
ZEN056V130A24LS
ZEN056V130A24LS
VOUT
ADJ
3
4
5
C64
C64
100nF
100nF
+
C65
C65
22uF
22uF
R89
R89
169K 1%
169K 1%
R92
R92
102K 1%
102K 1%
1
2
MN10
MN10
BNX002-01
BNX002-01
SV
SG
CG1
CG2
CG3
+
CV
C75
C75
100uF
100uF
SAM3S-EK Development Board User Guide
3
4
5
6
+3V3
C76
C76
100nF
100nF
+5V
DGND
+
C66
C66
22uF
22uF

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