AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 20

• Manufacturer Part Number: AT91CAP9A-STK
• Description: KIT STARTER FOR AT91CAP9A
• Manufacturer: Atmel
• Series: CAP™r
• Type: MCUr

Specifications of AT91CAP9A-STK

• Contents: Board, CD
• For Use With/related Products: AT91CAP9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.1.1.2 AT91CAP9 Clocks
2.4.1.2
2.4.1.2.1 FPGA Characteristics
AT91CAP9-STK Starter Kit User Guide
3V3
C102
10uF_1210
F2: FPGA and MPIO Bus
The internal clocks of the AT91CAP9 are generated by two external quartz sources:
This function is performed by an Altera Stratix2, EP2S15F484 FPGA and its EPCS16 serial configuration
device.
Stratix2 EP2S,15F484 FPGA characteristics are:
The FPGA aims to emulate the logic to be implemented in the MPB through 5 metal layers.
The FPGA also manages the EI14 interface.
For VDDBU, the choice is made by a jumper on the 3-pin J28 connector:
The implementation of VDDANA and VREEP is shown below.
12 Mhz quartz for the MAINCK internal clock
32,768 kHz quartz for the SLCK internal slow clock
15600 equivalent LE (LE is four-input LUT-based architecture),
1.2V core power supply, 3.3V or 1.8V I/O bank power supplies,
484-pin FBGA,
-5 speed grade.
C103
10nF
1
4,7µH 220mA
L6
2
C104
10uF_1210
J29
1X3PTS_MD_2MM54
1V2_SAVE
VDDANA
C105
10nF
J28
1V2
2
C99
10nF
VDDBU
4
1
3
U7
LM4120AIM5-3.0
C101
10nF
VIN
REF
EN
VOUT
5
6351B–CAP–27-Jun-08
Requirements
VREFP
C100
47nF
2-13