45300 Parallax Inc, 45300 Datasheet - Page 118

• Manufacturer Part Number: 45300
• Description: BOARD PROTO SX48
• Manufacturer: Parallax Inc
• Type: MCUr

Specifications of 45300

• Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SX48
• For Use With: 130-28029 - KIT PARTS SMART SENSORS45111 - MANUAL FOR SX-KEY/BLITZ VER. 2.028850 - CARRIER BOARD BOARD OF EDU USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

12 Appendix B: Instruction Set Overview
12.5 Instruction Set Quick Reference
This chart is a quick reference to command syntax, size, cycle time, CARRYX sensitivity and affected
flags and registers. An explanation of the abbreviations used, can be found on the next page.
Page 118 SX-Key/Blitz Development System Manual 2.0 Parallax, Inc.
Instruction
ADD
ADD
ADD
ADDB
AND
AND
AND
BANK
CALL
DEC
DECSZ
DJNZ
IJNZ
INC
INCSZ
IREAD
JB
JC
JMP
JNB
JNC
JNZ
JZ
MODE
MOV
MOV
MOV
MOV
CJA
CJAE
CJB
CJBE
CJE
CJNE
CLC
CLR
CLRB
CLZ
CSA
CSAE
CSB
CSBE
CSE
CSNE
JMP
[W|PC+W]
fr1,[#lit|fr2],addr9
fr1,[#lit|fr2],addr9
fr1,[#lit|fr2],addr9
fr1,[#lit|fr2],addr9
fr1,[#lit|fr2],addr9
fr1,[#lit|fr2],addr9
[fr|W|!WDT]
op.bit
fr1,[#lit|fr2]
fr1,[#lit|fr2]
fr1,[#lit|fr2]
fr1,[#lit|fr2]
fr1,[#lit|fr2]
fr1,[#lit|fr2]
fr,W
fr1,[#lit|fr2]
W,fr
fr,{/}op.bit
fr,W
fr1,[#lit|fr2]
W,[#lit|fr]
fr
addr8
fr
fr
fr,addr9
fr,addr9
fr
fr
op.bit,addr9
addr9
[addr9|W]
op.bit,addr9
addr9
addr9
addr9
lit
fr, W
fr1,[#lit|fr2]
fr,M
W,{/|++|--}fr
[PC|PC C DC Z]
[fr1 W|fr1 W Z]
[fr Z|W Z|(*1)]
fr1 W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
W C DC Z
fr C DC Z
MODE W
Table 25 - SX Instruction Set Quick Reference
Affects
fr1 W Z
fr Z PC
fr Z PC
op.bit
W Z
fr W
W Z
FSR
fr Z
fr Z
fr Z
fr Z
PC
PC
PC
PC
PC
PC
PC
PC
M
C
Z
fr
fr
fr
W C Instruction
1
2
1
2
1
2
1
1
1
4
4
4
4
4
4
1
1
1
1
3
3
3
3
3
3
1
1
2
2
1
1
1
2
2
1
1
2
2
2
2
1
1
2
2
1
4,6 MOV
4,6 MOVB
4,6 MOVSZ
4,6 NOP
4,6 NOT
4,6 OR
3,4 RETI
3,4 RETIW
3,4 RETP
3,4 RETW
3,4 RL
3,4 RR
1,2 SC
2,4 SETB
2,4 SKIP
1,2 SNB
2,4 SNZ
2,4 STC
2,4 SUB
2,4 SUBB
2,4 SWAP
2,4 SZ
1
2
1
2
1
2
1
1
3
1
1
1
1
1
1
4
3
3
1
1
2
2
1
MOV
MOV
MOV
MOV
MOV
MOV
OR
OR
PAGE
RET
SB
SLEEP
SNC
STZ
SUB
TEST
XOR
XOR
XOR
MOV
MOV
MOV
W,{<<|>>}fr
W,<>fr
W,[#lit|M]
M,fr
M,[#lit|W]
!OPTION,[fr|#lit]
!OPTION,W
!port,[fr|#lit]
!port,W
op1.bit1,{/}op2.bit2
W, [++|--]
[fr|W]
fr,W
fr1,[#lit|fr2]
W,[fr, #lit]
addr12
#lit{,#lit…}
fr
fr
op.bit
op.bit
op.bit
fr1,[#lit|fr2]
fr,W
fr,{/}op.bit
fr
[fr|W]
fr1,[#lit|fr2]
fr,W
W,[fr|#lit]
W,fr-W
[W Z !port|W !port]
[W Z OPT|W OPT]
C DC Z PAx PC W
fr1 W C DC Z
WDT TO PD
[fr Z|W Z]
W C DC Z
RTCC (*2)
fr C DC Z
!port (W)
PAx, PC
Affects
op1.bit1
fr1 W Z
fr1 W Z
W M Z
PC W
op.bit
none
W C
OPT
W Z
W Z
PAx
fr Z
fr C
fr C
fr Z
fr Z
PC
PC
PC
PC
PC
PC
PC
PC
W
W
M
W
C
Z
fr
Z
W
1
1
1
2
1
2
1
2
1
4
1
1
1
1
2
1
1
1
1
1
1
x
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
1
2
1
1
1
3*x
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
C
1
1
1
1
2
1
2
1
2
1
4
1
1
1
2
1
1
3
3
3
3
1
1
1
2
1
2
1
2
1
1
2
1
1