ST7MDT2-EPB2/US STMicroelectronics, ST7MDT2-EPB2/US Datasheet - Page 28

• Manufacturer Part Number: ST7MDT2-EPB2/US
• Description: BOARD PROGRAMMING SGL POS ST7
• Manufacturer: STMicroelectronics
• Type: MCUr

Specifications of ST7MDT2-EPB2/US

• Contents: Programmer Board
• For Use With/related Products: ST72311, ST72124, ST72314, ST72334
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST72334J/N, ST72314J/N, ST72124J
9.2 RESET SEQUENCE MANAGER (RSM)
9.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
Figure 15. Reset Block Diagram
28/153
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Delay depending on the RESET source
4096 CPU clock cycle delay
RESET vector fetch
RESET
Figure
14:
Figure
V
DD
R
ON
15:
f
CPU
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. RESET Sequence Phases
DELAY
4096 CLOCK CYCLES
INTERNAL RESET
RESET
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
VECTOR
FETCH