CML12C32SLK Freescale Semiconductor, CML12C32SLK Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
CML12C32SLK
Manufacturer Part Number
CML12C32SLK
Description
KIT STUDENT LEARNING 16BIT HCS12
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet
1.CML12C32SLK.pdf
(28 pages)
Specifications of CML12C32SLK
Contents
*
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
C M L - 1 2 C 3 2
Power Connectors
Power connectors J1 and TB1 provide power input to the board. Voltage input should be lim-
ited to the range of +6VDC to +16VDC with +9VDC typical. Voltage should be applied to the
board at either J1 or TB1 but not both. Applying input voltage to both input connectors at the
same time will cause a supply conflict and damage the CML-12C32 may result.
Connector J1 accepts a standard 2.1mm barrel plug connector with positive voltage center.
Connector TB1 accepts 18G – 24G solid copper wire. TB1 may also be used to gain access to
on-board power levels +Vin, GND, or +5VDC for off-board use. The +5VDC output may be
used to power off-board circuitry if desired. However, the voltage regulator output is internally
limited to 250 mA.
BUS_PORT
The BUS_PORT provides access to Port E signal and to latched address signals. Care should
be taken when using these signals. Excessive load may adversely affect MCU operation.
BDM PORT
The BDM port is a 6-pin header compatible with the Motorola Background Debug Mode (BDM)
Pod. This allows the connection of a background debugger for software development, pro-
gramming and debugging in real-time without using HC12 I/O resources.
A Background Debug Module is available from the Axiom Manufacturing.
PE6/MODB
PE0/XIRQ*
PE4/ECLK
PE2/RW*
BGND
POT 27
A10 21
A12 23
A14 25
NC
NC
A0 11
A2 13
A4 15
A6 17
A8 19
+5
1
3
5
7
9
1
3
5
10 GND
12 A1
14 A3
16 A5
18 A7
20 A9
22 A11
24 A13
26 A15
28 GND
2
4
6
8
2
4
6
PE1/IRQ*
PE3/LSTRB*
PE5/MODA
PR7/XCLKS*
GND
/RESET
+5V
See the HC12 Technical Reference Manual for
complete documentation of the BDM.
A[15..0] Latched Memory Addresses 0 to 15.
PE[7..0] MCU expanded bus control signals
13
J U L Y
2 6 ,
2 0 0 4