ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 63

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
8067M–AVR–09/10
Mnemonics
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external
2. One extra cycle must be added when accessing Internal SRAM.
RAM interface.
Operands
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
MCU Control Instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
SREG(s)
SREG(s)
I/O(A, b)
I/O(A, b)
Rd(n+1)
Rd(3..0)
Rd(0)
Rd(7)
Rd(n)
Rd(n)
Rd(b)
Operation
C
C
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
←
←
←
←
←
←
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
C,
Rd(n),
Rd(7)
C,
Rd(n+1),
Rd(0)
Rd(n+1), n=0..6
Rd(7..4)
1
0
1
0
Rr(b)
T
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XMEGA A1
Flags
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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