AT91EB40 Atmel, AT91EB40 Datasheet - Page 15

• Manufacturer Part Number: AT91EB40
• Description: AT91 ARM X40 SERIES EVAL KIT
• Manufacturer: Atmel

Specifications of AT91EB40

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.1
4.2
4.3
4.4
4.5
AT91EB40 Evaluation Board User Guide
AT91EB40 Top
Level
AT91R40807
Processor
I/O Expansion
External Bus
Interface
Power, Crystal
Oscillator and
Clock
Distribution
The top level schematic in Section 6, “Appendix B - Schematics” shows the blocks in
the system (see Figure 6-1). Each block is described in the appropriate section below.
This schematic shows the AT91R40807 (see Figure 6-7). The footprint is for a 100-pin
TQFP package.
Wirelink (WL2) can be removed by the user to allow measurement of the current
demand by the microcontroller.
The I/O expansion connector makes available to the user the general-purpose I/O
(GPIO) lines, VDD and ground. Surface mount links 5, 6, 7, 8 and 9 are used to select
between the I/O lines being used by the evaluation board or by the user via the I/O
expansion connector. The connector is not fitted at the factory; however, the user can fit
any 17 x 2 connector on a 0.1" (2.54 mm) pitch.
This schematic shows one AT29LV1024-15JC with a 128 KB 16-bit Flash and four
512K x 8 SRAM devices. See Figure 6-3.
Note:
The schematic also shows the bus expansion connector which, like the I/O expansion
connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1"
(2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator
output and wait state pins. Pin 8 on this connector can be used to apply an external
clock frequency to the board, assuming the clock select jumper is fitted accordingly (see
Section 5). VDD and ground are also available on the connector.
Switch 1 shown on this schematic is used to select either read-only access of all loca-
tions in Flash or allow read/write access to the top 64K bytes. This is to prevent the
Angel debug program, which is stored in the lower 64K bytes, from being erased.
The system clock is derived from a single 32.768 MHz crystal oscillator. This is divided
by a 4-bit binary counter to give alternate clock frequencies of 32.768 MHz divided by 2,
4 or 8. The system clock frequency is selected by fitting a jumper link in one position of
the link field (LK2) and details of this can be found in Section 5. One position in LK2
selects an external oscillator to be applied via the expansion bus interface.
Note that the 4-bit binary counter is not fitted at the factory; this function is optional.
The AT91EB40 is fitted with four 128K x 8 SRAM devices.
Circuit Description
Section 4
4-1