EVAL-AD1839AEB Analog Devices Inc, EVAL-AD1839AEB Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD1839AEB
• Description: BOARD EVALUATION FOR AD1839A
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front Endr

Specifications of EVAL-AD1839AEB

• Contents: Evaluation Board
• For Use With/related Products: AD1839A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CONTROL/STATUS REGISTERS
The AD1839A has 13 control registers, 11 of which are used to
set the operating mode of the part. The other two registers,
ADC Peak 0 and ADC Peak 1, are read-only and should not be
programmed. Each of the registers is 10 bits wide with the
exception of the ADC peak reading registers, which are 6 bits
wide. Writing to a control register requires a 16-bit data frame
to be transmitted. Bits 15 to 12 are the address bits of the
required register. Bit 11 is a read/write bit. Bit 10 is reserved and
should always be programmed to 0. Bits 9 to 0 contain the
10-bit value that is to be written to the register, or, in the case of
a read operation, the 10-bit register contents. Figure 15 shows
the format of the SPI read and write operation.
DAC Control Registers
The AD1839A register map has eight registers that are used to
control the functionality of the DAC section of the part. The
function of the bits in these registers is discussed next.
Sample Rate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC Control 3
should be programmed appropriately, based on the master clock
frequency.
Power-Down/Reset
This bit controls the power-down status of the DAC section. By
default, normal mode is selected; by setting this bit, the digital
section of the DAC stage can be put into a low power mode,
thus reducing the digital current. The analog output section of
the DAC stage is not powered down.
ADC NO. 1
ADC NO. 2
ADC NO. 3
SLAVE
SLAVE
SLAVE
LRCLK
LRCLK
LRCLK
MCLK
MCLK
MCLK
BCLK
BCLK
BCLK
DATA
DATA
DATA
12.288MHz
30MHz
Figure 27. Auxiliary Mode Connection (Slave Mode) to SHARC
DBCLK/AUXBCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
AAUXDATA3
MCLK
ASDATA
Rev. B | Page 19 of 24
SHARC
FSTDM
DAC Data-Word Width
These two bits set the word width of the DAC data. Compact
disk (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
DAC Data Format
The AD1839A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I
provided in the Serial Data Ports—Data Format section.
De-emphasis
The AD1839A provides built-in de-emphasis filtering for the
three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
Each of the six DACs in the AD1839A has its own independent
mute control. Setting the appropriate bit mutes the DAC output.
The AD1839A uses a clickless mute function that attenuates the
output to approximately −100 dB over a number of cycles.
Stereo Replicate
Setting this bit copies the digital data sent to the stereo pair
DAC1 to the three other stereo DACs in the system. This allows
all three stereo DACs to be driven by one digital data stream.
Note that in this mode, DAC data sent to the other DACs is
ignored.
DAC Volume Control
Each DAC in the AD1839A has its own independent volume
control. The volume of each DAC can be adjusted in 1,024
linear steps by programming the appropriate register. The
default value for this register is 1023, which provides no
attenuation, that is, full volume.
BCLK
2
S, LJ, RJ, or DSP modes. Details on these interface modes are
AD1839A
SLAVE
DSDATA1
DAUXDATA
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
LRCLK
BCLK
DATA
MCLK
DAC NO. 1
SLAVE
AD1839A