EVAL-AD1839AEB Analog Devices Inc, EVAL-AD1839AEB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD1839AEB
• Description: BOARD EVALUATION FOR AD1839A
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front Endr

Specifications of EVAL-AD1839AEB

• Contents: Evaluation Board
• For Use With/related Products: AD1839A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD1839A
Table 16. ADC Control 2
Address
15, 14, 13, 12
1101
Table 17. ADC Control 3
Address
15, 14,
13, 12
1110
CASCADE MODE
Dual AD1839A Cascade
The AD1839A can be cascaded to an additional AD1839A that,
in addition to six external stereo ADCs and two external stereo
DACs, can be used to create a 32-channel audio system with
16 inputs and 16 outputs. The cascade is designed to connect
to a SHARC DSP and operates in a time division multiplexing
(TDM) format. Figure 28 shows the connection diagram for
cascade operation. The digital interface for both parts must be
set to operate in Auxiliary 512 mode by programming ADC
Control Register 2. AD1839A Device 1 is set as the master
device by connecting the M /S pin to DGND; AD1839A
Device 2 is set as a slave device by connecting the M /S to
ODVDD. Both devices should be run from the same MCLK
and PD / RST signals to ensure that they are synchronized. With
R/W RES
11
0
R/W
0
11
RES
10
0
RES
10
0
9, 8
0, 0
Reserved
Master/Slave Aux Mode
9
0 = Slave
1 = Master
IMCLK Clocking Scaling
7, 6
00 = MCLK × 2
01 = MCLK
10 = MCLK × 2/3
11 = MCLK × 2
ADC Data Format
8, 7, 6
000 = I
001 = RJ
010 = DSP
011 = LJ
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
Rev. B | Page 22 of 24
2
S
ADC Peak Readback
5
0 = Disabled Peak Readback
1 = Enabled Peak Readback
Device 1 set as a master, it generates the frame-sync and bit
clock signals. These signals are sent to the SHARC and Device 2,
ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending DAC
data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers have been
clocked into the SHARC and replaced by DAC data, which is
subsequently written to the DACs. Figure 29 shows the timing
diagram for the cascade operation.
Function
11 = Reserved
ADC Data-
Word Width
5, 4
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
Function
AUXDATA
3
0 = Off
1 = On
DAC Test Mode
4, 3, 2
000 = Normal Mode
All Others Reserved
RES
2
0
Right
1
0 = On
1 = Mute
ADC Test Mode
1, 0
00 = Normal Mode
All Others Reserved
ADC MUTE
Left
0
0 = On
1 = Mute