EVAL-AD7686CB Analog Devices Inc, EVAL-AD7686CB Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD7686CB
• Description: BOARD EVALUATION FOR AD7686
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7686CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 15mW @ 500kSPS, 5 V
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7686
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7686
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7686 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7686 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
For example, when operating at 100 SPS, the device consumes
3.75 μW typically, which is ideal for battery-powered
applications.
The AD7686 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7686 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
This device is pin-for-pin-compatible with the AD7685,
AD7687, and AD7688.
GND
REF
IN+
IN–
32,768C
32,768C
16,384C
16,384C
MSB
MSB
Figure 24. ADC Simplified Schematic
4C
4C
Rev. B | Page 12 of 28
2C
2C
C
C
CONVERTER OPERATION
The AD7686 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase initiates. When the conversion phase begins,
SW+ and SW− are opened first.
The two capacitor arrays are then disconnected from the inputs
and connected to the GND input. Therefore, the differential
voltage between the inputs IN+ and IN−, captured at the end of
the acquisition phase, is applied to the comparator inputs,
causing the comparator to become unbalanced.
By switching each element of the capacitor array between GND
and REF, the comparator input varies by binary weighted
voltage steps (V
toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code and
a busy signal indicator. Because the AD7686 has an on-board
conversion clock, the serial clock, SCK, is not required for the
conversion process.
C
C
LSB
LSB
SW+
SW–
REF
COMP
/2, V
SWITCHES CONTROL
REF
/4 . . . V
CONTROL
LOGIC
CNV
REF
/65536). The control logic
BUSY
OUTPUT CODE