EVAL-AD7684CB Analog Devices Inc, EVAL-AD7684CB Datasheet - Page 14

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EVAL-AD7684CB

Manufacturer Part Number
EVAL-AD7684CB
Description
BOARD EVAL FOR AD7684 PCB
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of EVAL-AD7684CB

Number Of Adc's
1
Number Of Bits
16
Sampling Rate (per Second)
100k
Data Interface
Serial
Inputs Per Adc
2 Single
Input Range
±VREF
Power (typ) @ Conditions
4mW @ 5 V, 100kSPS
Voltage Supply Source
Single
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7684
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD7684
Table 9. Recommended Driver Amplifiers
Amplifier
ADA4841-x
ADA4941-1
AD8021
AD8022
OP184
AD8605,
AD8519
AD8031
VOLTAGE REFERENCE INPUT
The AD7684 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in more detail in the Layout section.
When REF is driven by a very low impedance source (for
example, an unbuffered reference voltage such as the low
temperature drift
the
chip capacitor is appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7684 powers down automatically at the end of each
conversion phase and therefore the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery
powered applications.
DIGITAL INTERFACE
The AD7684 is compatible with SPI, QSPI, digital hosts, and
DSPs (for example, Blackfin® ADSP-BF53x or ADSP-219x). The
connection diagram is shown in Figure 25, and the corresponding
timing is given in Figure 2.
1000
AD8031
0.01
100
0.1
10
1
10
AD8615
Figure 24. Operating Current vs. Sampling Rate
or the AD8605), a 10 μF (X5R, 0805 size) ceramic
ADR43x
100
Typical Application
Very low noise
Very low noise, single to differential
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power, and low frequency
High frequency and low power
SAMPLING RATE (SPS)
reference or a reference buffer using
VDD = 5V
1k
VDD = 2.7V
10k
100k
Rev. A | Page 14 of 16
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
low. The data bits are then clocked MSB first by subsequent
DCLOCK falling edges. The data is valid on both DCLOCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the DCLOCK falling edge allows a
faster reading rate, provided it has an acceptable hold time.
LAYOUT
The printed circuit board housing the AD7684 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7684 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7684 is
used as a shield. Fast switching signals, such as CS or clocks,
should never run near analog signal paths. Crossover of digital
and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In such a case,
it should be joined underneath the AD7684.
The AD7684 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7684 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7684. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE PERFORMANCE OF THE AD7684
Other recommended layouts for the AD7684 are outlined in the
evaluation board for the AD7684 (EVAL-AD7684CBZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
AD7684
DCLOCK
CS
Figure 25. Connection Diagram
D
OUT
EVAL-CONTROL
CONVERT
DATA IN
CLK
DIGITAL HOST
OUT
is enabled and forced
BRD3Z.

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