AD9380/PCB Analog Devices Inc, AD9380/PCB Datasheet - Page 27

• Manufacturer Part Number: AD9380/PCB
• Description: BOARD EVALUATION FOR AD9380
• Manufacturer: Analog Devices Inc

Specifications of AD9380/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hex
Address
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
Read/Write
or Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2:1]
[0]
[7]
[6]
[5]
[4]
[3]
[2:0]
[7:2]
[1:0]
[7:0]
[3:0]
[7:0]
[3:0]
[7:0]
[7]
[6:5]
[4:0]
Default
Value
******1*
*******0
0*******
*0******
**0*****
***0****
****1***
*****00*
*******0
1*******
*0******
**0*****
***0****
****0***
*****000
011000**
******01
00000100
****0101
00000000
****0010
11010000
0*******
*00*****
***11000
Register Name
Primary Output
Enable
Secondary Output
Enable
Output Three-State
SOG Three-State
SPDIF Three-State
I
Power-Down Pin
Polarity
Power-Down Pin
Function
Power-Down
Auto Power-Down
Enable
HDCP A0
MCLK External
Enable
BT656 EN
Force DE Generation
Interlace Offset
VS Delay
HS Delay MSB
HS Delay
Line Width MSB
Line Width
Screen Height MSB
Screen Height
Ctrl EN
I
I
2
2
2
S Three-State
S Out Mode
S Bit Width
Rev. 0 | Page 27 of 60
Description
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output Modes 1 and 2).
Three-state the outputs.
Three-state the SOG output.
Three-state the SPDIF output.
Three-state the I
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the power-down pin.
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto-low power state.
1 = enable auto-low power state.
Sets the LSB of the address of the HDCP I
second receiver in a dual-link configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
If an external MCLK is used, then it must be locked to the video
clock according to the CTS and N available in the I
match between the internal MCLK and the input MCLK results in
dropped or repeated audio samples.
Enables EAV/SAV codes to be inserted into the video output
data.
Allows use of the internal DE generator in DVI mode.
Sets the difference (in HSYNCs) in field length between Field 0
and Field 1.
Sets the delay (in lines) from the VSYNC leading edge to the start
of active video.
MSB, Register 0x29.
Sets the delay (in pixels) from the HSYNC leading edge to the
start of active video.
MSB, Register 0x2B.
Sets the width of the active video line in pixels.
MSB, Register 0x2D.
Sets the height of the active screen in lines.
Allows Ctrl [3:0] to be output on the I
00 = I
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
Sets the desired bit width for right-justified mode.
2
S mode.
2
S output and the MCLK out.
2
S data pins.
2
C. Set to 1 only for a
2
C. Any mis-
AD9380