AN2131-DK001 Cypress Semiconductor Corp, AN2131-DK001 Datasheet - Page 161
AN2131-DK001
Manufacturer Part Number
AN2131-DK001
Description
KIT EZ-USB DEVELOPMENT BOARD
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.AN2131SC.pdf
(334 pages)
Specifications of AN2131-DK001
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1333
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ISOCTL register bits shown as MBZ (must be zero) must be written with zeros. The
PPSTAT bit toggles every SOF, and may be written with any value (no effect). Therefore,
to disable the isochronous endpoints, the 8051 should write the value 0x01 to the ISOCTL
register.
8.9.2 Zero Byte Count Bits
When the SOF interrupt is asserted, the 8051 normally checks the isochronous OUT end-
point FIFOs for data. Before reading the byte count registers and unloading an isochro-
nous FIFO, the firmware may wish to check for a zero byte count. In this case, the 8051
can check bits in the ZBCOUT register. Any endpoint bit set to “1” indicates that no OUT
bytes were received for that endpoint during the previous frame. Figure 8-15 shows this
register.
The EZ-USB core updates these bits every SOF.
Page 8-16
ZBCOUT
Caution!
If you use this option, be absolutely certain that the host never sends isochronous data to
your device. Isochronous data directed to a disabled isochronous endpoint system will
cause unpredictable operation.
Note
The Autopointer is not usable from 0x2000-0x27FF (the reclaimed ISO buffer RAM)
when ISODISAB=1.
EP15
b7
EP14
b6
EP13
b5
Figure 8-15. ZBCOUT Register
Zero Byte Count Bits
Chapter 8. EZ-USB CPU
EP12
b4
EP11
b3
EP10
b2
EP9
b1
EZ-USB TRM v1.9
EP8
b0
7FA2
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