STV-974/552S-R01 STMicroelectronics, STV-974/552S-R01 Datasheet - Page 8

• Manufacturer Part Number: STV-974/552S-R01
• Description: KIT DEMO W/VS6552
• Manufacturer: STMicroelectronics

Specifications of STV-974/552S-R01

• Sensor Type: CMOS Imaging, Color (RGB)
• Sensing Range: VGA
• Interface: I²C
• Sensitivity: 30 fps
• Embedded: No
• Utilized Ic / Part: STV0974E, VS6552
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3891

VS6552
Figure 3. VS6552 Power-up Sequence
3.4.2 Active Signals with Unpowered VS6552
All signals going into the VS6552 must be either at
a low state or high impedance when power is re-
moved from the device. The exceptions to this rule
are the I
state and the clock which can be active.
3.5 Clock and Frame Rate Timing
3.5.1 Video Frame Rate Control
The output frame rate of VS6552 can be reduced
by extending the frame length. The extension is
achieved by adding 'blank' video lines to act as
timing padding. This is advantageous as it does
not reduce the pixel readout rate and therefore
does not introduce unwanted motion distribution
effects to the image. The frame rate can be re-
duced from the default 30 frame/s at VGA resolu-
tion to less than 3 frame/s at VGA resolution.
3.5.2 PLL and Clock Input
A PLL IP block is embedded. This block generates
all necessary internal clocks from an input range
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AVDD (2.8V)
VDD (1.8V)
PDATAP/N
PCLKP/N
MSDA
MSCL
2
PDN
CLK
C lines which may be at a low or high
and enable data qualification clock and
Mode Change: Sleep -> Clock active
general configuration
Standby
Sleep
Mode Change: Clock active -> Idle
Clock active
defined in
to 26 MHz signals.
Table 5. System Input Clock Frequency Range
3.5.3 Clock Input Type
VS6552 can receive the following clock types:
■
■
■
The clock is fail-safe.
Single ended CMOS
Single ended Sine wave
Clock can be AC or DC coupled
a.The standard supported input frequencies (in MHz) are as
Idle
Min. (MHz)
follows: 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2,
19.44, 26.
Mode Command: Idle -> Streaming
Table 5.
6.5
System clock frequency
also enable data output
The input clock pad accepts up
Streaming
Max. (MHz)
a
26