STV-974/552S-R01 STMicroelectronics, STV-974/552S-R01 Datasheet
STV-974/552S-R01
Specifications of STV-974/552S-R01
Related parts for STV-974/552S-R01
STV-974/552S-R01 Summary of contents
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... TFBGA low-footprint & lead-free package November 2004 Mobile Imaging DSP Description The STV0974 is a low power digital image processor designed for the VS6552 color VGA image sensor. The STV0974 uses advanced image processing techniques to deliver high quality VGA images frames per second (frame/s) ...
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... Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Chapter 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6.1 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Chapter 7 PCB layout guide lines for the STV0974 and VS6552 . . . . . . . . . . . . . . . . . . . .64 2/69 ...
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... Chapter 8 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Chapter 9 Evaluation kit and demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 3/69 STV0974 ...
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... Still features When requested by the baseband, the STV0974 captures bayer data from the sensor. Data is then color processed, down-scaled and/or compressed and sent through video output or microprocessor interface. In still mode, the first image produced has a guaranteed good exposure and color balance for single shot capture ...
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... Figure 1: Functional block diagram POR RST management PCLKP PCLKN PDATAP PDATAN MSCL MSDA STV0974 5/61 CLK PDN Clock & Power RAM - ROM Microprocessor Internal bus VC VisionLink serial receiver VP I2C master SCL I2C slave SDA Parallel interface and FIFO Mux DIO[0:13] Video output interface STV0974 ...
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... STV0974 3 Signal description Table 1: STV0974 signal description Pin name Power supplies VDD VCORE VDDPOR VSS Sensor interface PDATAP, PDATAN PCLKP, PCLKN MSDA MSCL Host interface POR RST CLK PDN DIO[0:11]DIO[13] DIO[12] SDA SCL Test interface (ST internal use) TMS TCK TDI TDO ...
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... Microprocessor interface In microprocessor interface mode, the data from the video processor or video compressor is stored in a FIFO. The interface informs the system via an IRQ or a DRQ that the FIFO is filling up. The system then has to pull some of the data from the STV0974 via the microprocessor interface. ...
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... The power-on-reset cell which output is the POR signal, is externally connected to the RST pin. Clocks In sleep mode, the STV0974 clock is derived from the clock signal applied to the CLK pin. In all other modes, the STV0974 clock is derived from the high speed clock received from the sensor ...
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... I²C compliant master controller, 1.8 V interface 400 kHz operation ● 4.2.2 Description The STV0974 sensor interface is dedicated to the VS6552 image sensor that uses the VisionLink data transfer protocol over vLVDS. This includes: An I²C master controller supporting 1.8 V interface and 400 kHz operation. The I²C master port ● ...
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... STV0974 4.3 Video processing unit 4.3.1 Features Low-power dedicated hardware video processing unit, pipeline operation up to VGA resolution ● Image sensor correction stage including pixel defect correction and fixed pattern noise (FPN) ● cancellation Color interpolation stage with anti-aliasing and color matrix compensation ● ...
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... RGB formats for viewfinder usage, as shown in Table 4 . 11/61 Cropping Scaling None None 528 x 432 / 1.5 82.5% of input image used, centered None / 2 528 x 432 / 3 82.5% of input image used, centered None / 4 None / 5 528 x 432 / 6 82.5% of input image used, centered Any Any See below STV0974 Comments ...
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... STV0974 Table 4: Output video formats Name UYVY RGB565 RGB444 RGB332 Byte ordering assumes a little endian memory system, i.e. in 16-bit formats, the least significant byte is sent first. For example, the UYVY format produces the sequence U Y Note: Nevertheless various options are available to suit memory system requirements: Byte ordering can be changed to big endian ● ...
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... The compression ratio can be modified by applying a multiplication factor on the quantization table. The quantization table can be scaled from a factor of 1 factor of 8. The STV0974 video compression block includes a baseline DCT JPEG encoder compliant with ISO DIS 10918-1. The JPEG encoder has the following characteristics: baseline sequential DCT based encoder ● ...
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... STV0974 4.4.1 Raster to block converter This block transforms the raster scan ordered data into block based ordered data. This data ordering is compliant with ISO DIS 10918-1 Annex A - Section A.2. Figure 4: Data sequence at Raster to block input pixel 1 line line The sequence of the input data stream is the following: line 1 from left to right up to pixel n, then line 2 from left to right ...
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... Y data of blockY2 of second MCU (64 data from left to right, then top to bottom) U data of blockU of second MCU (64 data from left to right, then top to bottom) V data of blockV of second MCU (64 data from left to right, then top to bottom) ... up to last image MCU. 15/61 MCU BlockU BlockY1 BlockY2 Figure 7 presents the structure of BlockY1 BlockY1 STV0974 V BlockV ...
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... STV0974 4.4.2 Discrete Cosine Transform This block performs a Discrete Cosine Transform on the incoming data stream compliant with ISO DIS 10918-1 Annex A - Section A.3. The block processes each 8x8 input block to transform them into 8x8 DCT coefficients. The calculation of the DCT coefficients is done by the formula: ...
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... Q’ uv Suv ⎛ Squv round ------------ = ⎝ Squeeze × ------------------------- Figure described in ISO DIS 10918-1 Annex 0.12 0.25 0.5 614 ~80 ~51 ~32 2.13 1.39 0.85 ⎞ ⎠ Quantization table for U and V blocks 0.62 1.25 1.87 ~27 ~21 ~12 0.72 0.56 0.32 STV0974 3.12 4. 0.24 0.24 ...
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... Number value) is Huffman encoded run contains more than 15 zeros, a specific number called ZRL is Huffman encoded. If all the values up to the end of the block are equal to zero, a specific code called EOB is Huffman encoded. Table 7 STV0974 output data stream Name SOI DQT ...
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... Huffman encoded, but the runlength counts them. When the first non-zero value is reached (Coefficient 4 with value 77), the Huffman code for the pair (number of preceding zeros, value) = (2,77) if Huffman encoded. The code that is generated is Code = Huffman (2,77). 19/61 DCT coefficient numbers in zigzag order Block Y2 data values STV0974 64 0 ...
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... Description The STV0974 can be connected to any general purpose 8-bit microprocessor via the microprocessor interface. This interface substitutes functionally to the YUV and I²C interfaces, i.e. both data and control flows are handled through the interface which provides: access to the image data FIFO for fast transfers of scaled-down viewfinder images or full- ● ...
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... X X The direct registers are used to access all STV0974 indirect registers and external image sensor registers through I²C. To read from a camera register: 1 Write AR with the indirect register address. 2 Poll the status register RDY bit until high. 3 Read the register data from DR. ...
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... FHTR. FRDY is level sensitive, i.e. it can be cleared only by reading FIFO. Ready: This bit indicates the state of the access request between the host and the STV0974 Register access in progress AR, DR and DW can be accessed by the host. For a read access, RDY is cleared upon host write to AR (MSB set by the micro- core when DR is updated with the register data. For a write access, RDY is cleared upon host write to DW ...
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... No data polling is required to access the microprocessor interface indirect registers. 23/61 Data Byte to write to camera subsystem. Data Byte read from the camera subsystem. FIFO read register. Microprocessor interface control register Interrupt mask register Interrupt clear register FIFO threshold register. FIFO count register. Description Description Table Description STV0974 ...
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... STV0974 FIFO Register (FIFO) FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the threshold. Reading from an empty FIFO returns the last valid byte read. ...
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... Each ICLR bit written with a ‘1’ clears the corresponding interrupt source bit in the status register (SR). Writing a ‘0’ has no effect - Reserved Holds the FIFO threshold value threshold = 1 threshold = Reserved Threshold value in 16-byte increments. Reserved Not Empty Force threshold to 1 (TH is ignored Normal Description Description Description (TH is ignored) (TH valid range is [1, 2...127]) Description STV0974 ...
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... Interrupt controlled transfer The STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs the following operations: 1 Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and detect the active interrupt sources. 2 Acknowledge pending interrupts by writing ICLR. ...
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... Finally, AR must be restored and the DMA controller released the end of the transfer, FIFO underrun can occur if the image size is not an integer multiple of the burst size: dummy bytes are appended at the end of the image buffer. Nevertheless, the JPEG end- of-frame marker (0xffd9) delineates the buffer. 27/61 STV0974 ...
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... STV0974 4.6 Video output interface 4.6.1 Video synchronization The STV0974 supports two modes of data stream synchronization. Either the data stream can be synchronized by separate HSYNC and VSYNC signal (see codes in the data stream (see 4.6.2 Synchronization codes Horizontal synchronization The horizontal synchronization signal can be embedded within the data ...
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... Figure 16: Timings with associated qualifying clocks Data[7:0] YCbCr HCLK Data[7:0] RGB565 RGB444 HCLK Data[7:0] RGB332 HCLK 29/ Active Active lines Blanking Un,n+1 Yn Pix0_lsb Pix0_msb Pix0 Figure 15 . SAV EAV Blanking Figure 16 , with the associated Vn,n+1 Yn+1 Un+2,n+3 Pix2_lsb Pix2_msb Pix3_lsb Pix1 Pix2 STV0974 ...
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... STV0974 4.6.5 JPEG data on 8-bit parallel with qualification clock This interface outputs JPEG on parallel 8-bit IOs. Different synchronization can be provided, as Figure 17 described in There are no defined lines in a JPEG data stream. The whole stream is output as a single frame line with VSYNC and HSYNC asserted together. ...
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... Power management unit The STV0974 is reset via the internal PowerOnReset cell (POR) or via an external control reset line. The device reset is controlled by the RST pin. The POR cell generates an output signal on the POR pin every time that the device external supply is switched off or the PDN pin is activated ...
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... STV0974 Figure 20: Boot-up phase machine VDD t1 PDN RST POR Clk Mode Timing constraints: Table 21: Timing constraints Note compatible with external power-on/internal power-down modes (ex: external VDD on and PDN low), all input pads from baseband side as well as SCL and SDA pads on both sensor and baseband sides are “ ...
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... This block generates all the necessary internal clocks from an input range defined in input clock pad accepts MHz signals. Table 22: System input clock frequency range Min. (MHz) a. Standard supported input frequencies (in MHz): 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26 33/61 System clock frequency 6.5 STV0974 Table 22 a Max. (MHz The ...
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... STV0974 4.9 Camera control unit 4.9.1 Features User mode transition ● register map including high-level registers and low-level registers dedicated to scaler ● control 4.9.2 Description Figure 21: State machine user mode transitions VDD Power down Sleep PDN: Power Down pin i. the “1” transition is automatic ii ...
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... Goto VF or Goto Live Sleep Go to clk Set Get sensor active external clock Clock Active Sleep t0: Time to interpret Mode change command (< 1ms) t1: Time to set clk characteristics (< 1ms) t2: Time to get sensor characteristics (< 3ms idle t2 Idle Go to Idle characteristics Idle Clock Active STV0974 ...
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... Time to interpret Mode change command (< 1ms) t1: Time to set VF or Live parameters inside the STV0974 and to send VF or Live settings to the sensor (~2ms) t2: Time to go from Idle to Video Active state (Sensor side) t3: Exposure time (Sensor side). It depends on the frame rate. Goto Idle ...
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... The system (exposure, white balance) is already stable in viewfinder mode. The user settings are sent to the sensor. The processed frame is sent after a short latency. 2 The system has not stabilized. STV0974 enters transient mode and, when stable, automatically goes into Capture mode. 37/61 below ...
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... STV0974 Once the image is sent, the STV0974 automatically returns to Idle. See Figure 27: Viewfinder to capture timing SCL/SDA capture ViewFinder 974 mode STV0974 output data MSCL/MSDA Sensor mode VisionLink data Note the system exposure and white balance is already stable, the maximum delay is 1 frame. ...
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... Functional description 4.9.3 I²C register map Register interpreter The STV0974 I²C address is 0x08. The addressing space is defined in Table 23: Fields of address map Index Bit [12-8] [7-0] The customer accessible register map is divided into groups as listed in Table 24: Register groups Group Register group [0] Register group [1] ...
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... STV0974 There are restrictions related to the states at which registers can be accessed. state coding used in the register description. Table 25: Register state coding State code Register contents represent different data types as described in Table 26: Type of data State Code Registers listed as reserved or read-only should NOT be written to, as this may cause unpredictable results ...
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... Bit [15:11]: Integer part Bit [10:0]: Decimal part (1 unit = 1/ 2048 MHz) i.e. default value is 26MHz. b Sensor clock derating [15-0]: Reserved [15]: Booting [14-7]: Reserved [6]: Flash [5]: Capture in progress [4]: Live [3]: Capture [2]: Viewfinder [1]: Idle [0]: Sleep [15-7]: Reserved [6]: Flash [5]: Reserved [4]: Live [3]: Capture [2]: Viewfinder [1]: Idle [0]: Sleep STV0974 status ( Table 10 ) ...
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... STV0974 Table 27: System and status [register group 0] Name Index Input / Output 0xA00A Protocol Control a. See Clock input section, for standard external clock frequencies supported. b. The product limitation in derating mode Half Speed -> Max I2C clock is 200 kHz 4: Quarter Speed -> Max I2C clock is 100 kHz ...
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... Still and Live 0xA101 Output Image Size Still and Live 0xA102 Output Image Format Still Multi-frames 0xA103 Transfer Mode Delay transfer 0xA104 Mode Viewfinder Frame 0xA105 Rate a (STV0974 input) Viewfinder Image 0xA106 Size 43/61 State Data Format R/W code type default R DDDD.DDDD 0011.1100 ...
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... STV0974 Table 28: Image characteristics [Register group 1] Name Index Viewfinder Image 0xC107 Format a. The corresponding frame rates are considered as targets. If the target cannot be achieved due to derated sensor clock or output format versus output protocol, the closest possible frame rate is achieved, knowing that 30 frame/s is the highest frame rate supported by the device. ...
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... R RRRR.RRRD 1111.1101 R RDDD.DDDD 0011.1110 STV0974 Description Correction in tens of percentage 0: 0% 10: 100%, >10: Frozen Bit[7]: Defect correction matrix (default is square matrix) Bit(6]: Defect correction enable (correction of bad pixels) Bit[5]: Defect scythe enable (Smooth filtering of good pixels) Bit[4:3]: Defect scythe rank ...
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... STV0974 Register group 3 Table 30: Color management [register group 3] Name Index Still / live Gamma 0xA300 Standard Gain Still / live Gamma 0xA301 S-Curve gain Still / live Gamma 0xA302 Misc. Viewfinder 0xA303 Gamma Standard Gain Viewfinder 0xA304 Gamma S-Curve gain Viewfinder 0xA305 Gamma Misc. ...
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... A I RRRR.DDDD 0000.0001 R DDDD.DDDD 0000.0000 R DDDD.DDDD 0000.0000 R DDDD.DDDD 0000.0000 STV0974 Description AC Frequency in Hz Zone weight: [3]: Reserved [2]: Backlit [1]: Centered [0]: Flat One unit of compensation is equivalent to 1/3 EV. Default value is equivalent to 0 EV. [Default - 2] is equivalent to -2/3 EV. Valid range Description [15-9]: Reserved [8]: Reserved [7]: Reserved [6]: Reserved [5]: Reserved ...
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... STV0974 Register Group 6 Table 33: Flash mode management [register group 6] Name Index Torch polarity 0x8A43 Torch control 0x8A44 Flash pulse 0x8A45 polarity Flash pulse length 0x88D4 Note: Access to the bits mentioned here above is done through a read-modify-write sequence example, when torch mode is set: ...
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... DDDD.D000 1000.0000 R RRRR.RRDD 0000.0001 R DDDD.D000 1110.0000 STV0974 ” or “ Viewfinder Image Description X-coordinates of the centre of the source image window. Default is 322 Y-coordinates of centre of the source image window. Default is 242 Width of the destination image (after scaling) in viewfinder mode. The value must be a multiple of 8 pixels ...
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... STV0974 Table 34: Scaler low-level control Name Index Still / Live Scaling 0x806D factor Note: If the scaling factor it too high and the cropped image size is bigger than the full source image, the scaling factor is automatically set to the closest possible high value. MMS Downscale zoom This section contains an example of how the low level scalar registers can be used to implement a down scale ‘ ...
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... Scale by 3 from 480x360 crop 6. Scale by 4 from 640x480 crop Zoom factor = 1.6 Zoom factor = 1.333 Zoom factor = 1 6. Troubleshooting Sensor not responding. Need to go back to Idle. Re-grab new image One of the requested JPEG frames is larger than the target. User to restart capture command STV0974 ...
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... Please contact ST support for patch delivery and recommendations for ideal use. 4.10 Additional features There are a number of additional features which are supported by the STV0974, however implementation of these features is not supported by this datasheet. Please contact the ST support team for support of these features if you have a specific requirement. ...
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... Supply voltage DD T Ambient temperature A 5.3 Thermal data Symbol Rth(j-a) Junction-ambient thermal resistance - TFBGA56 a. Typical, measured with the component mounted on an evaluation PC board in free air. 53/61 Parameter Parameter Parameter a STV0974 Value Unit -0.5 to +2 100 mA ±10 mA -40 to 150 °C +260 ° ...
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... STV0974 5.4 DC electrical characteristics Over operating conditions unless otherwise specified. Symbol Parameter V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage OH I Input leakage current IL Input pins I/O pins C Input capacitance IN SCL, MSCL C Input / Output capacitance ...
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... DH a. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum capacitance on both SDA and SCL. 55/61 Figure 30 ) Parameter 1/f CLK Figure 31 ) Parameter a a STV0974 Min. Typ. Max. 1.7 1.8 1.9 6 Min. Typ. Max. 400 1.3 ...
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... Please contact ST for details. b. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum capacitance on both MSDA and MSCL LOW HD.DAT HIGH SU.DAT value driven by the STV0974. t HD.DAT. DH Parameter Electrical characteristics Start t HD.STA ...
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... Electrical characteristics 2 Figure 32 master timing Stop Start SDA t BUF SCL t HD.STA the same timing when the host is driving. 57/ LOW HD.DAT HIGH SU. value driven by the STV0974. t HD.DAT. DH Start t HD.STA SU.STA is the value HD.DAT STV0974 Stop SU.STO ...
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... STV0974 5.5.4 Video output timing Table 41: Video output timing ( Symbol t Data and synchro setup time DS t Data and synchro hold time DH t Clock pulse width high CKH t Clock period CKP t Clock rise time CKR a. with capacitance Figure 33: Video output timing hclk ...
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... VisionLink serial receiver timing Table 43: VisionLink serial receiver input timing ( Symbol t Data setup time DS t Data hold time DH t Clock period CKP 59/61 RS CSN RDN t RACC CSN WRN Figure Parameter RREC RDH WREC t WDH t WDS 36) Min. Typ. Max. 1 2.7 8.3 STV0974 Unit ...
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... STV0974 Figure 36: VisionLink basic input timing PCLK PDATA Table 44: Receiver VisionLink / SubLVDS electrical characteristics Symbol V Input common mode voltage range I V Input differential threshold IDTH (Va -Vaz) t Power-up/-down time PWRUP/ PWRDN Parameter Electrical characteristics t CKP Min Typ Max 0.4 0.4 +/-50 +/-200 ...
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... Package mechanical data 6 Package mechanical data 6.1 Pin assignment Figure 37: STV0974 pin assignment 61/ VSS DIO2 DIO1 DIO0 RST POR VDD NC NC TMS VSS TDI NC NC VCORE VSS PCLKP PDATAP PDATAN PCLKN VSS VDD VSS VCORE VSS DIO3 DIO4 DIO5 VDD DIO6 ...
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... STV0974 6.2 Package dimensions Table 45: TFBGA 6x6x1.20 56 2R10 0.50 - Package dimensions Reference ddd d .eee e .fff a. Max mounted height is 1.20mm. Based on a 0.27mm ball pad diameter. Solder paste is 0.15mm thickness and 0.27mm diameter. b. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. ...
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... Package mechanical data Figure 38: TFBGA 56 6x6x1.2 2R10 0.5 seating plane C 63/ corner index area (see note (56 balls) bottom view STV0974 ...
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... To save components, 100 Ω termination resistors are embedded in the high speed subLVDS signal pairs (PCLKP/PCLKN) and (PDATAP/PDATAN) of the STV0974. All passive components for the STV0974 should be placed in close proximity to the device, including the decoupling capacitors. The decoupling capacitors for the VS6552 should be placed close to the sensor ...
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... Application schematics 8 Application schematics Figure 39: Mobile camera application, 8-bit parallel video interface, V 65/61 STV0974 = 2.8V with low level shifter I/O ...
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... STV0974 Figure 40: Mobile camera application, microprocessor interface, V Application schematics = 1.8V, no low level shifter I/O 66/61 ...
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... The demonstration boards are small kits that do not allow hard connections to the customers system. Table 46: Ordering details Part Number STV-974-/552S-E01 STV-974/552S-R01 STV-974/552S-R02 67/61 Evaluation kit including base board, STV0974 plug in, flex attached VS6552 plug-in and socketed VS6552 plug-in ...
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... Section 3: Signal description : Added precisions about internal resistor for PDATAP/N and PCLKP/N Electrical characteristics : Modified I DDP PCB layout guide lines for the STV0974 and VS6552 embedded termination resistors in the STV0974. Minor revision. Format update. Revision history Functional description . I²C register map ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 69/69 The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics. All Rights Reserved. STMicroelectronics Group of Companies http://www.st.com STV0974 ...