ADC12062EVAL National Semiconductor, ADC12062EVAL Datasheet - Page 9

• Manufacturer Part Number: ADC12062EVAL
• Description: BOARD EVALUATION FOR ADC12062
• Manufacturer: National Semiconductor

Specifications of ADC12062EVAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12062EVAL

Connection Diagrams
Pin Descriptions
AV
DV
AGND,
DB0–DB11
V
MUX OUT
IN1
CC
CC
, V
IN2
These are the two positive analog supply
inputs. They should always be connected to
the same voltage source, but are brought out
separately to allow for separate bypass ca-
pacitors. Each supply pin should be by-
passed to AGND with a 0.1 µF ceramic ca-
pacitor in parallel with a 10 µF tantalum
capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AV
be bypassed to DGND2 with a 0.1 µF ce-
ramic capacitor in parallel with a 10 µF tan-
talum capacitor.
DGND1,
DGND2
These are the power supply ground pins.
There are separate analog and digital ground
pins for separate bypassing of the analog
and digital supplies. The ground pins should
be connected to a stable, noise-free system
ground. All of the ground pins should be
returned to the same potential. AGND is the
analog ground for the converter. DGND1 is
the ground pin for the digital control lines.
DGND2 is the ground return for the output
databus. See Section 6.0 LAYOUT AND
GROUNDING for more information.
These are the TRI-STATE output pins, en-
abled by RD, CS, and OE.
These are the analog input pins to the multi-
plexer. For accurate conversions, no input
pin (even one that is not selected) should be
driven more than 50 mV below ground or 50
mV above V
This is the output of the on-board analog
input multiplexer.
Top View
CC
.
CC
. It should
01149013
9
ADC IN
S0
MODE
CS
INT
EOC
RD
OE
S/H
This is the direct input to the 12-bit sampling
A/D converter. For accurate conversions,
this pin should not be driven more than 50
mV below AGND or 50 mV above AV
This pin selects the analog input that will be
connected to the ADC12062 during the con-
version. The input is selected based on the
state of S0 when EOC makes its high-to-low
transition. Low selects V
V
This pin should be tied to DV
This is the active low Chip Select control
input. When low, this pin enables the RD,
S/H, and OE inputs. This pin can be tied low.
This is the active low Interrupt output. When
using the Interrupt Interface Mode ( Figure 1 ),
this output goes low when a conversion has
been completed and indicates that the con-
version result is available in the output
latches. This output is always high when RD
is held low ( Figure 2 ).
This is the End-of-Conversion control output.
This output is low during a conversion.
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data ap-
pears on the data bus. This pin can be tied
low.
This is the active high Output Enable control
input. This pin can be thought of as an in-
verted version of the RD input (see Figure 6 ).
Data output pins DB0–DB11 are TRI-STATE
when
DB0–DB11 only when OE is high and CS
and RD are both low. This pin can be tied
high.
This is the Sample/Hold control input. The
analog input signal is held and a new conver-
IN2
.
OE
Top View
is
low.
Data
IN1
CC
, high selects
appears
.
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CC
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