CLC5958PCASM National Semiconductor, CLC5958PCASM Datasheet - Page 10

• Manufacturer Part Number: CLC5958PCASM
• Description: EVALUATION BOARD FOR CLC5958
• Manufacturer: National Semiconductor

Specifications of CLC5958PCASM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC5958PCASM

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CLC5958 Application Information
The transformer converts the single-ended clock signal to a
differential signal. The center-tap of the secondary is biased
by the V
secondary limit the input swing to the buffer.
Since the encode inputs are close to the analog inputs, it is
recommended that the analog inputs be routed on the top of
the board directly over a ground plane and that the encode
lines be routed on the back of the board and then connected
through via to the encode inputs.
Latching the Output Data
The rising edge of DAV is approximately centered in the data
transition window, and may be used to latch the output data.
The DAV output has twice the load driving capability of the
data outputs so that two latch clock inputs may be driven by
this output.
Routing Output Data Lines
It is recommended that the ground plane be removed under
the data output lines to minimize the capacitive loading of
these lines. In some systems this may not be permissible
because of EMI considerations.
Harmonics and Clock Spurious
Harmonics are created by non-linearity in the track-and-hold
and the quantizer. Harmonics that arise from repetitive
non-linearities in the quantizer may be reduced by the appli-
cation of a dither signal.
Transformers and baluns can contribute harmonic distortion,
particularly at low frequencies where transformer operation
relies on magnetic flux in the core. If a transformer is used to
perform single ended to differential conversion at the input,
care should be taken in the selection of the transformer.
The clock is internally divided by the CLC5958 in order to
generate internal control signals. These divided clocks can
contribute spurious energy, principally at fs/4 and fs/8. The
clock spurious is typically less than −90 dBFS.
Calibration Sidebands
The CLC5958 incorporates on-board calibration. The cali-
bration process creates low level sideband spurious close to
the carrier and near DC for some input frequencies. In most
applications these sidebands will not be an issue. The side-
bands add negligible power to the carrier and therefore do
not reduce sensitivity in receiver applications. Also, the side-
bands never fall in adjacent channels with any appreciable
power. They may be visible in some very narrow-band ap-
plications, and so are documented here for completeness.
The offset of the sidebands relative to the carrier and relative
to DC is derived using the equations:
where f is the sideband offset, f
is the sample rate, and round ( • ) denotes integer rounding.
The magnitude of the sideband relative to the carrier for a full
scale input tone is approximated by the equations
(Continued)
BB
potential of the ECL buffer. The diodes in the
IN
is the input frequency, f
01501923
S
10
where a is the sideband magnitude relative to the input, and
off 2 dB per dB as the input amplitude is reduced.
For example, assume the input frequency is 4.8671 MHz
and the sample rate is 52 MSPS. Then the sideband offset is
derived as follows:
If the input is a full scale input, then the magnitude of the
sidebands is derived as:
The sidebands roll off rapidly with increasing sideband off-
set. For example, if the sideband is offset 200 kHz from the
carrier (in an adjacent GSM channel) as opposed to the
7.9 kHz offset from the previous example, the sideband
magnitude is reduced to −116 dBc.
Figure 4 shows how the sideband offset frequency varies
with input frequency at a sample rate of 52 MSPS.
The sideband magnitude is a function of the sideband offset,
as illustrated in Figure 5 .
is the calibration sideband coefficient. The value of
FIGURE 4. Sideband Offset vs. Input Frequency
01501927
01501925
01501924
01501926
rolls