C8051F000DK-A Silicon Laboratories Inc, C8051F000DK-A Datasheet - Page 106
C8051F000DK-A
Manufacturer Part Number
C8051F000DK-A
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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CP0OEN
Bit7:
Bit6:
Bits3-5: PCA0ME: PCA Module I/O Enable Bits
Bit2:
Bit1:
Bit0:
R/W
Bit7
0: CP0 unavailable at Port pin.
1: CP0 routed to Port Pin.
ECIE: PCA0 Counter Input Enable Bit
0: ECI unavailable at Port pin.
1: ECI routed to Port Pin.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port Pin.
010: CEX0, CEX1 routed to 2 Port Pins.
011: CEX0, CEX1, CEX2 routed to 3 Port Pins.
100: CEX0, CEX1, CEX2, CEX3 routed to 4 Port Pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to 5 Port Pins.
110: RESERVED
111: RESERVED
0: UART I/O unavailable at Port pins.
1: RX, TX routed to 2 Port Pins.
0: SPI I/O unavailable at Port pins.
1: MISO, MOSI, SCK, and NSS routed to 4 Port Pins.
0: SMBus I/O unavailable at P0.0, P0.1.
1: SDA routed to P0.0, SCL routed to P0.1.
CP0OEN: Comparator 0 Output Enable Bit
UARTEN: UART I/O Enable Bit
SPI0OEN: SPI Bus I/O Enable Bit
SMB0OEN: SMBus Bus I/O Enable Bit
ECIE
R/W
Bit6
Figure 15.3. XBR0: Port I/O CrossBar Register 0
R/W
Bit5
PCA0ME
R/W
Bit4
Rev. 1.7
R/W
Bit3
UARTEN
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SPI0OEN
R/W
Bit1
SMB0OEN
R/W
Bit0
SFR Address:
Reset Value
00000000
0xE1
106
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