C8051F000DK-A Silicon Laboratories Inc, C8051F000DK-A Datasheet - Page 158
C8051F000DK-A
Manufacturer Part Number
C8051F000DK-A
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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20.1.4. Pulse Width Modulator Mode
All of the modules can be used independently to generate pulse width modulated (PWM) outputs on their respective
CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of
the PWM output signal is varied using the module’s PCA0CPLn capture/compare register. When the value in the
low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will
be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 20.6). Also, when
the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the
value stored in the PCA0CPHn without software intervention. It is good practice to write to PCA0CPHn instead of
PCA0CPLn to avoid glitches in the digital comparator. Setting the ECOMn and PWMn bits in the PCA0CPMn
register enables Pulse Width Modulator mode.
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
Figure 20.6. PCA PWM Mode Diagram
0
ENB
ENB
1
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
O
G
T
n
P
W
M
n
E
C
C
F
n
x
PCA Timebase
Enable
Rev. 1.7
PCA0CPHn
PCA0CPLn
Comparator
PCA0L
8-bit
Overflow
match
S
R
SET
CLR
Q
Q
CEXn
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Crossbar
Port I/O
158
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