HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 227

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6.9
Event
Operand access count
Internal I/O access count
Cache miss count
TLB miss count
Instruction fetch count
Branch count
Instruction execution
count
Interrupt count
Cache fill cycle count
Elapsed time count
Note: For the non-cache operand accesses due to the PREF instruction or TLB.c=0, the correct
The events can be counted even in the conditions shown in table 6.10, in addition to the normal
count conditions.
value cannot be counted.
Measurement Events
Keyword
OARW*
OARAM
OA
IOA
DCRW
EC
DT
ET
EF*
EA
B
BT
E
E2
EFP
ETR
INT
NMI
ECF
OCF
TM
Description
The number of times the operand access is performed on
the cacheable area when the cache is enabled (both read
and write accesses).
The number of times the internal RAM area is accessed.
The number of all operand accesses.
The number of times the internal I/O is accessed.
The number of times operand cache misses occur at data
reading or writing.
The number of times instruction cache misses.
The number of times UTLB misses occur at data access.
The number of times UTLB and ITLB misses occur at
instruction access.
The number of times instructions are fetched from the
cacheable area when the cache is enabled.
The number of times all instructions are fetched.
The number of times branch instructions are issued
(instructions to be counted: BF (other than displacement 0),
BF/S, BT (other than displacement 0), BT/S, BRA, BRAF,
JMP).
The number of times branches are taken (branches to be
counted are the same as mode B).
The number of times instructions are issued.
The number of times two instructions are issued at the
same time.
The number of times FPU instructions are issued.
The number of times the TRAPA instruction is executed.
The number of interrupts except NMI.
The number of NMI interrupts.
The number of instruction cache fill cycles.
The number of operand cache fill cycles.
The number of cycles for elapsed time.
Rev. 2.0, 01/01, page 203 of 214