SI5318-EVB Silicon Laboratories Inc, SI5318-EVB Datasheet - Page 16

• Manufacturer Part Number: SI5318-EVB
• Description: BOARD EVALUATION FOR SI5318
• Manufacturer: Silicon Laboratories Inc
• Type: Precision Clockr

Specifications of SI5318-EVB

• Contents: Fully Assembled Evaluation Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SI5318
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1179

Si5318
2.3.3. Jitter Tolerance
Jitter tolerance for the Si5318 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency, because tolerance
improves for lower input jitter frequency. See Figure 7.
2.4. Digital Hold of the PLL
When no valid input clock is available, the Si5318
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is again valid. This clock maintains very
stable operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 8.
2.5. Hitless Recovery from Digital Hold
When the Si5318 device is locked to a valid input clock,
a loss of the input clock causes the device to
automatically switch to digital hold mode. When the
input clock signal returns, the device performs a
“hitless” transition from digital hold mode back to the
selected input clock. That is, the device performs
“phase build-out” to absorb the phase difference
between the internal VCO clock operating in digital hold
mode and the new/returned input clock. The maximum
phase step size seen at the clock output during this
transition and the maximum slope for this phase step
are given in Table 4 on page 8.
This feature can be disabled by asserting the
FXDDELAY pin. When the FXDDELAY pin is high, the
output clock is phase and frequency locked with a
known
Consequently, any abrupt phase change on the input
clock propagates through the device, and the output
slews at the selected loop bandwidth until the original
phase relationship is restored.
Note: When the DBLBW is asserted, hitless recovery must
16
Am plitude
10 ns
Input
Jitter
Figure 7. Jitter Tolerance Mask/Template
also be disabled by driving FXDDELAY high for proper
operation.
phase
–20 dB/dec.
relationship
Excessive Input Jitter Range
F
BW
to
the
input
clock.
f
Jitter In
Rev. 1.0
2.6. Loss-of-Signal Alarm
The Si5318 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this
divided-down input clock to search for extended periods
of time without input clock transitions. If the LOS
circuitry detects four consecutive samples of the
divided-down input clock that are the same state (i.e.,
1111 or 0000), a LOS condition is declared, the Si5318
goes into digital hold mode, and the LOS output alarm
signal is set high. The LOS sampling circuitry runs at a
frequency of f
frequency when the FRQSEL[1:0] pins are set to 10.
Table 3 on page 7 lists the minimum and maximum
transitionless time periods required for declaring a LOS
on the input clock (t
Once the LOS alarm is asserted, it is held high until the
input clock is validated over a time period designated by
the VALTIME pin. When VALTIME is low, the validation
time period is about 100 ms. When VALTIME is high,
the validation time period is about 13 s. If another LOS
condition is detected on the input clock during the
validation time (i.e., if another set of 1111 or 0000
samples are detected), the LOS alarm remains
asserted, and the validation time starts over. When the
LOS alarm is finally released, the Si5318 exits digital
hold mode and locks to the input clock. The LOS alarm
is automatically set high at power-on and at every low-
to-high transition of the RSTN/CAL pin. In these cases,
the Si5318 undergoes a self-calibration before releasing
the LOS alarm and locking to the input clock.
Figure 8. Recovery from Digital Hold
O_155/2
LOS
, where f
Recovery from
Digital Hold
).
m
O_155
PT
is the output clock
t
t
PT_MTIE