HIP4082EVAL Intersil, HIP4082EVAL Datasheet - Page 6

• Manufacturer Part Number: HIP4082EVAL
• Description: EVAL BOARD FET DRIVER HIP4082
• Manufacturer: Intersil
• Type: FET Driverr

Specifications of HIP4082EVAL

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: HIP4082
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The energy required to charge a capacitor to a certain
voltage and discharge it to its original voltage level is the
product of the capacitance and the voltage attained across
the capacitor during the charging cycle. The AC snubber
dissipation is therefore:
f
PWM modulation technique was avoided, namely that the
snubber power would have been quite substantial. The charge
transferal in the DC bus snubber is almost negligible, because
the capacitor voltage doesn’t appreciably change or switch
polarities like that of the AC snubber. Therefore the power
rating of the DC snubber’s series resistor can be minimal
(1/4W in this design).
Between the output banana jacks BJ
high voltage inverter a bifilar-wound choke was placed in
order to reduce conducted EMI at the load. Capacitor C
aids in this regard.
Secondary Inverter Control Circuits
Simplicity and cost-effectiveness were the major design
goals. A feed-forward voltage regulation approach was
chosen to regulate the load RMS voltage within roughly 10%
over the expected load and battery input swings so as to
avoid the expense, complexity and stability problems
associated with a feedback approach. By using a
transformer with low secondary reflected resistance, most of
the regulation problem is limited to a “line regulation”
problem (battery changes from 10V
opposed to a “load regulation” problem.
To accomplish the regulation function using the filtered DC
bus voltage as a measured parameter, it was necessary to
determine the relationship between required duty cycle as a
function of the battery voltage which would result in an output
voltage of 115V
graphed and indicated that as the battery voltage increased,
the width of the positive and negative half-cycles should get
smaller, but the duty cycle reduction should be less than
proportionally reduced as the battery voltage increased. A
2
1
PWM
FIGURE 4. SECONDARY-SIDE PHASE NODE WAVEFORMS
CH1 = 100V
= 55Hz. This fact is one reason that a high frequency
AC(RMS)
CH2 = 100V
V
to the load. The function was
BUS
2
M = 2.5µs CH2
6
×
C
SNUBBER
DC
3
to 15V
and BJ
×
f
DC
PWM
4
64V
, and the
) as
Application Note 9611
, where
C2 (MAX)
172V
C1 FREQ.
56.024kHz
LOW
SIGNAL
AMPL.
13
ramp which had positive curvature (i.e., positive first
derivative) would be able to synthesize this function where the
amount of positive curvature depended on the amount of
desired reduction in the duty-cycle. Figure 5 shows the
waveform necessary to produce the desired regulation
compensation.
The upper trace, Trace 2, is the triangle wave which is
compared with a reference signal proportional to the DC bus
voltage. When the triangle wave exceeds the reference
value, a clock pulse, Trace 1, is generated. The rising edge
of the clock pulse coincides with the moment that the triangle
wave becomes greater than the reference value proportional
to DC bus voltage.
When the DC bus voltage decreases, the reference wave
decreases, and the rising edge of the clock pulse advances
as shown in Figure 6.
The important point to remember is that as the DC bus
voltage decreases, the rising clock pulse occurs earlier and
earlier.
Also notice that the clock pulse frequency is double that of
the desired output frequency of the inverter, namely 110Hz
rather than 55Hz which is the desired excitation frequency to
the load. Figure 7 shows the clock waveform, TP
and the associated Q (or QNOT) signal from flip-flop U
(Trace 2). The Q and QNOT waveforms are inverted from
each other at half the clock signal frequency and are
responsible for driving the phase-shifted half-bridge
comprised of MOSFETs Q
A similar clock pulse (not shifted) coming from pin 3 of U
produces an identical set of conditions on the Q and QNOT
outputs of flip-flop, U
LIN (TP
side half-bridge). An identical set of signals will be seen at the
HIN and LIN inputs of the stationary (left side) half-bridge
driver, TP
stationary half-bridge comprised of MOSFETs Q
2
1
FIGURE 5. SECONDARY-SIDE CONTROL WAVEFORMS
CH1 = 5V
17
19
) inputs of the phase-shifted half-bridge driver (right
and TP
CH2 = 2V
20
5A
, respectively, responsible for driving the
. Figure 8 shows the HIN (TP
7
M = 2.5µs
and Q
9
.
GLITCH CH2
6
10
and Q
(Trace 1),
18
C2 FREQ.
110.496Hz
) and
5B
8
8
.