DS1678K Maxim Integrated Products, DS1678K Datasheet - Page 4

• Manufacturer Part Number: DS1678K
• Description: KIT EVAL RT EVENT RECORD DS1678
• Manufacturer: Maxim Integrated Products

Specifications of DS1678K

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
I
2
SDA
C COMMUNICATION TIMING DIAGRAM
SCL
STOP
Limits at -40C are guaranteed by design and not production tested.
All voltages referenced to ground.
After this period, the first clock pulse is generated.
A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge
A fast-mode device can be used in a standard-mode system, but the requirement t
C
t
t
of SCL. The maximum t
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
line is released.
pulldown capacitor.
BU F
R
B
and t
START
—Total capacitance of one bus line in pF.
F
are measured with a 1.7kΩ pullup resistor, 200pF pullup capacitor, 1.7kΩ pulldown resistor, and 5pF
t
H D:STA
t
LOW
t
R
HD:DAT
t
H D:D AT
need only be met if the device does not stretch the LOW period (t
t
HIG H
t
F
t
SU :DA T
4 of 25
t
SU:STA
REPEATED
START
t
R(MAX)
HD:STA
+ t
SU:DAT
SU:DAT
> 250ns must then be met. This is
= 1000 + 250 = 1250ns before the SCL
LOW
) of the SCL signal.
t
SU:STO