DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet
DS-FND-BSX-PC
Specifications of DS-FND-BSX-PC
Related parts for DS-FND-BSX-PC
DS-FND-BSX-PC Summary of contents
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Foundation Series 2.1i User Guide Foundation Series 2.1i User Guide 1- Introduction 2 - Project Toolset 3 - Design Methodologies - Schematic Flow 4 - Schematic Design Entry 5 - Design Methodologies - HDL Flow 6 - HDL Design Entry ...
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... The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ...
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5,790,882; 5,795,068; 5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016; 5,815,404; 5,815,405; 5,818,255; 5,818,730; 5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845; 5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577; 5,847,579; 5,847,580; ...
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Foundation Series 2.1i User Guide Foundation Series 2.1i User Guide Appendix A - Glossary Appendix B - Foundation Constraints Appendix C - Instantiated Components Appendix D - File Processing Overview ...
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... Resource Tutorial Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm Answers Current listing of solution records for the Xilinx software tools Database Search this database using the search function at http://support.xilinx.com/support/searchtd.htm Foundation Series 2.1i User Guide Description/URL ...
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Foundation Series 2.1i User Guide Resource Application Descriptions of device-specific design techniques and approaches Notes http://support.xilinx.com/apps/appsweb.htm Data Book Pages from The Programmable Logic Data Book, which describe device- specific information on Xilinx device characteristics, including read- back, boundary scan, configuration, ...
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... Appendix C, “Instantiated Components,” lists the components most frequently instantiated in synthesis designs. • Appendix D, “File Processing Overview,” contains diagrams of the file manipulations for FPGAs and CPLDs during the design process. Foundation Series 2.1i User Guide About This Manual ™ ...
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Foundation Series 2.1i User Guide iv Xilinx Development System ...
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... However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0]. rpt_del_net= Courier bold also indicates commands that you select from a menu. File • ...
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Foundation Series 2.1i User Guide • • Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required. edif2ngd [option_name] design_name • Braces “{ }” enclose a list of items ...
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Introduction This chapter contains the following sections. • “Architecture Support” • “Platform Support” • “Foundation Demo” • “Tutorials” • “Online Help” • “Books” Architecture Support Foundation supports the following Xilinx device families. • XC3000A/L • XC3100A/L • XC4000E/L/EX/XL/XV/XLA • XC5200 ...
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... Xilinx Foundation Series On-Line Help System. The umbrella help contains topics covering all of the design entry and implementation tools provided in the product plus additional infor- mation. It also contains in-depth information essential for designing with FPGAs and CPLDs, including the following topics: • CPLD design techniques • ...
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Reference information on the HDL languages, CPLD schematic library and attributes, and Foundation configurations You can invoke the “umbrella” help system (shown in the following figure) by selecting Help Project Manager menu bar. Figure 1-1 The Online “Umbrella” Help ...
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Foundation Series 2.1i User Guide Books Multiple printed and online books are available for the Foundation Series 2.1i product and the various tools included with it. Printed Books The Foundation Series 2.1i Installation Guide and Release Notes describes installation procedures, ...
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Foundation-Specific Online Books The following online books contain information that applies only to the Xilinx Foundation Series products. Title Foundation Series 2.1i Quick Start Guide Foundation Series 2.1i User Guide Verilog Reference Guide VHDL Reference Guide Foundation Series 2.1i User ...
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Foundation Series 2.1i User Guide Design Entry Online Reference Books The following books contain additional information not found in the Foundation-specific books regarding the Xilinx schematic library components (and constraints) and LogiBLOX. Title Libraries Guide LogiBLOX Guide Note: The CORE ...
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Implementation-Related Online Books The following books contain detailed information on the Xilinx implementation tools. Much of the information contained in these books is for the standalone or command line versions of the tool. Title Constraints Editor Guide Design Manager/ Flow ...
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... Description This manual describes the Xilinx Demonstration hardware and its associated software interfaces. The hardware includes the FPGA and CPLD demonstration boards, which are used for design verification. This manual describes Xilinx’s Timing Analyzer program, a graphical user interface tool that performs static analysis of a mapped FPGA or CPLD design ...
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Contents About This Manual Additional Resources ..................................................................... i Manual Contents ............................................................................ ii Conventions Typographical................................................................................. v Online Document ........................................................................... vi Chapter 1 Introduction Architecture Support ...................................................................... 1-1 Platform Support ............................................................................ 1-2 Foundation Demo........................................................................... 1-2 Tutorials ......................................................................................... 1-2 Online Help .................................................................................... 1-2 ...
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Foundation Series 2.1i User Guide Files Tab ........................................................................................ 2-9 Versions Tab........................................................................ 2-10 Project Flowchart Area.............................................................. 2-10 Flow Tab - Project Flowchart ............................................... 2-10 Alternatives to Flowchart Buttons ........................................ 2-11 Contents Tab ....................................................................... 2-11 Reports Tab ......................................................................... 2-11 Synthesis Tab (Schematic ...
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FPGA Editor......................................................................... 2-22 CPLD ChipViewer................................................................ 2-22 Automatic Pin Locking ......................................................... 2-22 Device Programming...................................................................... 2-23 JTAG Programmer.................................................................... 2-23 PROM File Formatter................................................................ 2-23 Hardware Debugger.................................................................. 2-23 Utilities............................................................................................ 2-24 Schematic Symbol Library Manager ......................................... 2-24 Command History ..................................................................... 2-24 Project Notes ............................................................................ 2-25 ...
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Foundation Series 2.1i User Guide Defining States.......................................................................... 3-21 Defining Transitions, Conditions, and Actions .......................... 3-22 Adding a Top-Level ABEL Design to the Project ...................... 3-22 Chapter 4 Schematic Design Entry Managing Schematic Designs........................................................ 4-1 Design Structure ....................................................................... 4-2 Single Sheet ...
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Performing HDL Behavioral Simulation (Optional).................... 5-5 Synthesizing the Design ........................................................... 5-5 Express Constraints Editor ....................................................... 5-8 Express Time Tracker............................................................... 5-10 Performing Functional Simulation ............................................. 5-12 Implementing the Design .......................................................... 5-15 Editing Implementation Constraints .......................................... 5-17 Verifying the Design.................................................................. 5-20 Performing ...
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... Symbolic and Encoded State Machines ................................... 7-4 Compromises in State Machine Encoding ................................ 7-5 Binary Encoding........................................................................ 7-5 One-Hot Encoding .................................................................... 7-6 One-Hot Encoding in Xilinx FPGA Architecture................... 7-6 Limitations............................................................................ 7-6 Encoding for CPLDs ................................................................. 7-7 Chapter 8 LogiBLOX Setting Up LogiBLOX ....................................................... 8-2 Starting LogiBLOX ......................................................................... 8-2 Creating LogiBLOX Modules.......................................................... 8-4 LogiBLOX Modules ...
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Basic Functional Simulation Process ............................................. 10-1 Invoking the Simulator .............................................................. 10-1 Attaching Probes (Schematic Editor Only)................................ 10-2 Adding Signals .......................................................................... 10-2 Creating Buses ......................................................................... 10-3 Applying Stimulus ..................................................................... 10-3 Stimulator Selection Dialog.................................................. 10-3 Waveform Test Vectors ....................................................... 10-4 Script File ...
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... Implementation Reports ................................................................. 11-26 Translation Report .................................................................... 11-28 Map Report (FPGAs) ................................................................ 11-28 Place and Route Report (FPGAs)............................................. 11-28 Pad Report (FPGAs)................................................................. 11-29 Fitting Report (CPLDs).............................................................. 11-29 Post Layout Timing Report ....................................................... 11-29 Additional Implementation Tools .................................................... 11-29 Constraints Editor ..................................................................... 11-29 Flow Engine Controls................................................................ 11-30 Controlling Flow Engine Steps............................................. 11-30 Running Re-Entrant Routing on FPGAs ...
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A-1 Aldec .............................................................................................. A-1 aliases ............................................................................................ A-1 analyze........................................................................................... A-2 architecture .................................................................................... A-2 attribute .......................................................................................... A-2 binary encoding.............................................................................. A-2 BitGen ............................................................................................ A-2 Black Box Instantiation................................................................... A-2 block............................................................................................... A-2 breakpoint ...................................................................................... A-3 buffer .............................................................................................. A-3 bus ................................................................................................. A-3 CLB ................................................................................................ A-3 ...
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Foundation Series 2.1i User Guide hierarchical designs ....................................................................... A-9 Hierarchy Browser.......................................................................... A-9 implementation............................................................................... A-9 Implementation Constraints Editor ................................................. A-9 instantiation .................................................................................... A-9 Language Assistant........................................................................ A-9 Library Manager ............................................................................. A-9 locking ............................................................................................ A-10 LogiBLOX....................................................................................... A-10 logic................................................................................................ A-10 Logic Simulator .............................................................................. A-10 ...
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A-16 state machine................................................................................. A-16 state machine designs ................................................................... A-16 states.............................................................................................. A-16 static timing analysis ...................................................................... A-16 static timing analyzer...................................................................... A-16 status bar ....................................................................................... A-17 stimulus information ....................................................................... A-17 Symbol Editor................................................................................. A-17 Synopsys........................................................................................ A-17 synthesis ........................................................................................ A-17 Time ...
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Foundation Series 2.1i User Guide Converting a Logical Design to a Physical Design ................... B-16 “Last One Wins” Resolution ...................................................... B-17 XC5200XL Constraints ............................................................. B-17 Efficient Use of Timespecs and Layout Constraints....................... B-18 The “Starter Set” of Timing Constraints .................................... ...
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... BSCAN Component ....................................................................... C-4 READBACK Component................................................................ C-5 RAM and ROM............................................................................... C-6 Global Buffers ................................................................................ C-8 Fast Output Primitives (XC4000X only) ......................................... C-10 IOB Components............................................................................ C-11 Clock Delay Components............................................................... C-13 Appendix D File Processing Overview FPGAs............................................................................................ D-1 CPLDs............................................................................................ D-4 Foundation Series 2.1i User Guide Contents xxi ...
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Foundation Series 2.1i User Guide xxii Xilinx Development System ...
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Project Toolset This chapter explains how to create Foundation projects and how to access the various Foundation tools that you use to complete the project. Each tool and its function is briefly described. This chapter contains the following sections. • ...
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... HDL Flow project. If you are using the Base (DS-FND- BAS-PC) or Standard (DS-FND-STD-PC) products, only the Sche- matic Flow is available to you. Both flows are available to Base Express (DS-FND-BSX-PC) and Foundation Express (DS-FND-EXP- PC) users. Schematic Flow Projects A Schematic Flow project can have top-level schematic or ABEL files. ...
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Enter the project name characters, in the Name field of the New Project dialog box. 4. Select a location for the project in the Directory box. 5. Select F2.1i as the project type in the Type ...
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Foundation Series 2.1i User Guide • On the left side is the Hierarchy Browser consisting of a hierarchy tree of the project files on the Files tab and of the project imple- mentation versions on the Versions tab. • The ...
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HDL Flow Projects (Express Only) An HDL Flow project can contain VHDL, Verilog, or schematic top- level designs with underlying VHDL, Verilog, or schematic modules. HDL files can be created by the HDL Editor, Finite State Machine Editor, or other ...
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Foundation Series 2.1i User Guide 4. Select a location for the project in the Directory box. 5. Select F2.1i as the project type in the Type box. 6. Select the HDL Flow. Note: When you select the HDL Flow button, ...
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... The Project Manager performs the following functions: • Automatically loads all design resources when opening a project • Checks that all project resources are available and up-to-date • Illustrates the design process flow Foundation Series 2 ...
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Foundation Series 2.1i User Guide • Initiates applications used in the design process • Displays error and status messages in the message window • Provides automated data transfer between various Foundation design tools • Displays design status information The three ...
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Files Tab The Files tab displays the hierarchy of the project files, project libraries, and external files. From this tab you can add, remove, or reorder the displayed files and libraries as well as open applications associated with them. For ...
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Foundation Series 2.1i User Guide Extension .v .vhd .abl .asf .ucf .tve For detailed information about the project files, libraries, and other project information, refer to the online help by selecting Help Foundation Help Contents Information. Versions Tab The Versions ...
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HDL Flow project (see the “Project Manager - Schematic Flow” figure and the “Project Manager - HDL Flow” figure). When you start programs from the project flowchart, the Project Manager automatically controls the transfer of input and output data ...
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Foundation Series 2.1i User Guide Messages Area The tabs included in the Messages area display general project messages and specific HDL processing messages. Console Tab The Console tab displays the contents of the project log. HDL Errors Tab (HDL Flow ...
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Accessing the CORE Generator System The Xilinx CORE Generator is a graphical interactive tool that generates and delivers parameterizable cores optimized for Xilinx FPGAs. You can access the CORE Generator system from the Project Manager by selecting Tools Generator or ...
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Foundation Series 2.1i User Guide netlists and files for each revision. Therefore, if you want to save iter- ations of the source design (schematics, HDL files, for example), you must back those up yourself. Foundation 2.1i also supports archiving of ...
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Board-level and PLD schematic support (requires the Active- CAD tool) • Export of schematic netlists to XNF, EDIF, VHDL, and Verilog formats • Integration with synthesis design tools (HDL Editor and State Diagram editor) • Integration with the Logic ...
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Foundation Series 2.1i User Guide • Language templates with basic language constructs • Synthesis templates of functional blocks such as counters, flip- flops, multiplexers, and Xilinx architectural features such as Boundary Scan and RAM For detailed information about the HDL ...
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Graphical constraints editor. The Express Constraints Editor GUI is available to Foundation Express users only used to set design constraints and view estimated design performance. Synthesis Tab (Schematic Flow Schematic Flow project, the necessary synthesis ...
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Foundation Series 2.1i User Guide timing requirements. It creates timing analysis reports that you customize by applying filters. It organizes and displays data that allows you to analyze the critical paths in your circuit, the cycle time of the circuit, ...
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Constraints Editors Two Constraints Editor GUIs are available in Foundation to assist with constraining elements of your design to obtain the desired performance. Express Constraints Editor (HDL Flow) The Express Constraints Editor is a feature available in the Founda- tion ...
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... Constraints, and Carry Logic” chapter of the Libraries Guide. The User Constraints File (UCF user-created ASCII file that holds the constraints. You can enter the constraints directly in the input design. However, putting them in the UCF separates them from the input design files and provides for easier modification and reduces re-synthesis of your design ...
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Floorplanner File The Floorplanner tool generates an MFP file that contains mapping and placement information. You can use ...
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Foundation Series 2.1i User Guide an FPGA implementation revision. For more information on the Floorplanner, see the Floorplanner Guide, an online book. FPGA Editor Selecting Tools Project Manager window opens the FPGA Editor. The FPGA Editor provides a graphic view ...
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... PROM File Formatter. For CPLD designs, you must use the JTAG Programmer. JTAG Programmer The JTAG Programmer downloads, reads back, and verifies FPGA and CPLD design configuration data. It can also perform functional tests on any device and probe the internal logic states of your design. ...
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Foundation Series 2.1i User Guide Utilities Foundation contains multiple utilities to help you manage and orga- nize your project. Those available from the Project Manager’s Tools Utilities menu are described below. Schematic Symbol Library Manager The Library Manager allows you ...
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An option to display the date and time for each command is also available. Project Notes Project Notes (Tools standard text editor of your choice in which you can make notes ...
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Foundation Series 2.1i User Guide 2-26 Xilinx Development System ...
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Design Methodologies - Schematic Flow This chapter describes various design methodologies supported in the Schematic Flow project subtype. This chapter contains the following sections. • “Schematic Flow Processing Overview” • “Top-Level Designs” • “All-Schematic Designs” • “Schematic Designs with Instantiated ...
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... HDL, CORE Generator Optional Yes Add Hierarchy? No Functional Simulation (Analyze Logic) Reports Netlist Translation Xilinx Constraints Editor Map (FPGA) or FIT (CPLDs) Analyze Timing Place and Route (FPGAs only) Timing Simulation Analyze Timing Create Bitsream Reports Download Bitstream Design Entry Implementation Programming ...
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Top-Level Designs Schematic Flow projects can have top-level schematic or Finite State Machine (ABEL) designs. A top-level design can have any number of underlying schematic, HDL, LogiBLOX, CORE Generator, ABEL, or Finite State Machine (FSM) macros. Although individual modules may ...
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Foundation Series 2.1i User Guide Performing Functional Simulation 1. Open the Logic Simulator by clicking the Functional Simulation icon in the Simulation box on the Project Manager’s Flow tab. The design is automatically loaded into the simulator. The Wave- form ...
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Verify that the output waveform is correct. Click the Step button repeatedly to continue simulating. 10. To save the stimulus for future viewing or reuse, select File Save Waveform. Enter a file name with a .tve extension in the ...
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Foundation Series 2.1i User Guide shown in the Implement Design dialog box. You can modify the version and revision names as desired the Implement Designs dialog box, select Set. The Settings dialog box appears. 4. Specify control files ...
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... Project Create Revision. This accesses the Create Revision dialog box that has the same fields as the Implement Design dialog box. The revision name is automatically entered. Modify the names, control files, and/or options and run the Flow Engine as described previ- ously for the first version/revision ...
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... If you want to implement a new version of the design (after the initial implementation), you must first create the new version by selecting Project dialog box that has the same fields as the Implement Design dialog box. The version name is automatically entered. Modify the names, control files, and/or options and run the Flow Engine as described previously for the first version/revision ...
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... The following figure shows an example of the Global tab of the Implementation Constraints Editor. 2. Design-specific information is extracted from the design and displayed in device-specific spreadsheets. Click the tabs to access the various spreadsheets. Foundation Series 2.1i User Guide Design Methodologies - Schematic Flow Constraints Editor from the Project ...
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... Foundation Series 2.1i User Guide 3. Right-click on an item in any of the spreadsheets to access a dialog box to edit the value. Use the online help in the dialog boxes to understand and enter specific constraints and options. Or, refer to the online software document, Constraints Editor Guide for detailed information. ...
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... For FPGAs, you can perform a post-MAP or post-place timing analysis to obtain rough timing information before routing delays are added. You can also perform a post-implementation timing analysis on CPLDs after a design has been implemented using the CPLD fitter. For details on how to use the Timing Analyzer, select Help dation Help Contents Performing a Timing Simulation 1 ...
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Foundation Series 2.1i User Guide 2. The Waveform Viewer window displays on top of the Logic Simulator window. Refer to the “Performing Functional Simulation” section for instructions on simulating the design. (The operation of the simu- lator is the same ...
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... Create a macro symbol by selecting Project from the HDL Editor window. The synthesizer will not insert top level input and output pads for this macro. Instead the top level schematic, which contains the Foundation Series 2.1i User Guide Design Methodologies - Schematic Flow ...
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... Foundation Series 2.1i User Guide macro, includes all top level input and output pads required for implementation. For more information about creating HDL macros, from the Project Manager window, select Help Contents Creating the Schematic and Generating a Netlist 1. Open the Schematic Editor by clicking the Schematic Editor icon in the Design Entry box on the Project Manager’ ...
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Schematic Designs With Instantiated LogiBLOX Modules LogiBLOX modules can be used in schematic designs. First, the module must be created. The module can then be added to the sche- matic like any other library component. Creating LogiBLOX Modules To use ...
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Foundation Series 2.1i User Guide To convert an existing LogiBLOX module to a binary netlist and save the component to the project working library, perform the following steps the Schematic Editor, select Tools 2. From the Import LogiBLOX ...
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Options dialog box. The Family entry should reflect the project’s target device. Click OK to exit the Project Options dialog box aid selection, the available Cores are categorized in folders on the View Mode section of the main ...
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Foundation Series 2.1i User Guide • “Implementing the Design” • “Verifying the Design” • “Programming the Device” Schematic Designs With Finite State Machine (FSM) Macros This section explains how to create state machine macros and instantiate them in schematic designs. ...
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... The synthesizer will not insert top level input and output pads for this macro. Instead the top level schematic, which contains the macro, includes all top level input and output pads required for implementation. For more information about state machines, select Help ...
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Foundation Series 2.1i User Guide • “Implementing the Design” • “Verifying the Design” • “Programming the Device” Finite State Machine (FSM) Designs The FSM Editor allows you to specify functionality using the "bubble state diagram" concept. Once you have described ...
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... Select Next. 6. Define your ports in the Design Wizard-Ports window. Select Next the Design Wizards - Machines window, select the number of State Machines that you want. Click Finish. The Wizard creates the ports and gives you a template in which you can enter your macro design. 8. ...
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Foundation Series 2.1i User Guide 10. Define the transition, conditions, and actions for the state diagram. 11. When you have completed the state diagram, select File Save. Defining Transitions, Conditions, and Actions Transitions define the changes from one state to ...
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Schematic Design Entry This chapter contains the following sections: • “Managing Schematic Designs” • “Hierarchical Schematic Designs” • “Manually Exporting a Netlist” • “Creating a Schematic from a Netlist” • “Miscellaneous Tips for Using the Schematic Editor Tool” Refer to ...
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... Multi-sheet designs • Hierarchical designs Selecting a structure depends on the design size (number of symbols and connections), purpose (board or chip design), and company standards. The following sections describe each of these design types. Single Sheet Schematic Single sheet designs are typically used for small designs. The largest page size is 44” ...
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... Since large number of symbols are used in FPGA and CPLD designs, handling large designs using the multi-sheet design structure can become very difficult and complex. Large designs typically require thousands of simple primitives like gates and flip-flops. To simplify schematics, designers prefer to use high-level components that have Foundation Series 2.1i User Guide ...
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Foundation Series 2.1i User Guide clear functionality. These high-level components are implemented using hierarchical macros. A hierarchical macro, a device in the library that looks like a standard component, is implemented as a symbol with an underlying schematic or netlist. ...
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... Netlist names can become very long because you must specify the complete hierarchical path. The method used to create unique reference identifiers adds the hierarchy reference name to each symbol reference. For example, a symbol U58 in a macro called H8 will be called H8/U58. In multilevel hierarchical designs, these names can become very long depending on the number of hierarchy levels ...
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... Add Sheets to Project. In the Add to Project window, select the schematic file(s) you want to add and click the Add button. The sche- matic editor loads each added sheet and verifies that the symbols used in these schematics are available and that there are no duplicate reference numbers ...
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Note: Deleting the sheet from the project does not delete the schematic file from the disk. If you want to delete unwanted files, you can use the Windows Explorer and delete *.SCH files from the project directory. Renumbering Symbol References ...
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Foundation Series 2.1i User Guide Copying a Section of a Schematic to Another Sheet If you want to move or duplicate a section of a schematic to another sheet, perform the following steps: 1. Place the cursor at the corner ...
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... Input, Output, or Bidirectional. This specification is impor- tant because the design entry tools automatically generate a symbol. The location of the pins on the symbol depends upon their schematic I/O definition (only inputs are on the left- side of the symbol outline). If needed, edit this symbol in the Symbol Editor ...
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Foundation Series 2.1i User Guide Recognizing Hierarchical Macros You can recognize hierarchical macro symbols by their color. By default, the schematic-based macros are dark blue. The netlist-based macros are purple. You can change these default colors by selecting View Navigating ...
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If you double click on a symbol that does not have an underlying schematic, HDL, or FSM file, the following message displays: Symbol is a primitive cell. To exit the H cursor mode, select Hierarchy You can also navigate the ...
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... Foundation Series 2.1i User Guide Note: Double clicking on the top schematic name or the name of any of its underlying schematic macros loads that schematic to the screen for viewing and editing. Modifying Existing Macros If you want to make some changes to an existing macro schematic, perform the following steps: 1 ...
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Difference between a Macro and a Schematic The following example explains what happens with the hierarchical schematic when you create a macro. Assume that the project TEST contains the schematic sheets TEST1 and TEST2. Create a macro for the schematic ...
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Foundation Series 2.1i User Guide 3. In the Design Wizard - Contents dialog box, choose Schematic in the Contents section. Enter the Symbol Name and then select Next the Design Wizard - Ports dialog box, select New. 5. ...
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Draw the schematic shown in the“MACROS1 Schematic” d) Use the Hierarchy Connector icon (shown below) to draw the e) Connect the symbols (Mode f) Figure 4-1 MACROS1 Schematic 3. Create the MACROS1 symbol. a) Select Hierarchy Foundation Series 2.1i ...
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Foundation Series 2.1i User Guide b) Click OK. The netlist and the MACROS1 schematic are saved 4. Create the second schematic (MACROS2). a) Select File b) Select the Symbol mode in the schematic toolbar. In the SC c) Draw the ...
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Save the schematic using File 5. Create the MACROS2 symbol. a) Select Hierarchy b) Click OK. The netlist and the MACROS2 schematic are saved c) Save the schematic using the Save option. 6. Create a new sheet for the ...
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Foundation Series 2.1i User Guide 7. Use the Push/Pop option to view schematics. Select Hierarchy H displays. Point the cursor at the Symbol H1 and double click the mouse button. The schematic ONE opens showing you the schematic of the ...
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From the File of Type pulldown menu, select the desired format. 3. Choose the source netlist ALB file. By default, the project netlist is automatically selected. 4. Click OPEN to start exporting. Note: The EDIF netlist format is recommended ...
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... Select the page size to be used for the generated schematics. The smaller the page size you select, the more numerous are the sche- matic files that are generated. 5. Select Landscape or Portrait. 6. Select Wireless to implement all connections using the connect- by-name method. ...
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... Using Input and Output Buffers Xilinx schematics require that you use input and output buffers between input and output pads. The following figures illustrate incorrect and correct input and output port design. Figure 4-3 Incorrect Port Design (Without Buffers) Figure 4-4 Correct Port Design (With Buffers) ...
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Foundation Series 2.1i User Guide Note the LOCK1 and LOCK2 tabs in the lower left corner of the figure. Clicking on the LOCK2 tab navigates to the LOCK2 schematic sheet. For every new schematic sheet added to the design, a ...
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Design Methodologies - HDL Flow This chapter describes various design methodologies supported in the HDL Flow project subtype. This chapter contains the following sections. • “HDL Flow Processing Overview” • “Top-level Designs” • “All-HDL Designs” • “HDL Designs with State ...
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... Express Constraints (Elaborate) Editor Enter Constraints Optimize Functional Simulation Express Time Tracker Analyze Timing Reports Implementation Netlist Translation Map (FPGAs) or Fit (CPLDs) Analyze Timing Place and Route (FPGAs only) Timing Simulation Analyze Timing Create Bitsream Reports Programming Download Bitstream Design Entry Synthesis ...
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Top-level Designs HDL Flow projects do not require the designation of a top-level design until synthesis. VHDL, Verilog, and schematic files can be added to an HDL Flow project. VHDL and Verilog source files can be created by the HDL ...
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Foundation Series 2.1i User Guide 5. From the Design Wizard - Language window, select VHDL or Verilog. Click Next. Note: For top-level ABEL designs, you must use the Schematic Flow the Design Wizard - Name window, enter the ...
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Performing HDL Behavioral Simulation (Optional) If you installed an HDL simulation tool such as ACTIVE-VHDL or ModelSIM, you can perform a behavioral simulation of your HDL code. Please refer to the documentation provided with these tools for more information. Synthesizing ...
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Foundation Series 2.1i User Guide 3. Click the Synthesis icon on the Synthesis button on the Flow tab. 4. The Synthesis/Implementation dialog box is displayed if this is the first version and revision of a project. (By default on subse- ...
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... GUI. For more information refer to the “Express Time Tracker” section. Modify the target clock frequency Select the optimization strategy as speed or area Select the effort level as high or low Select whether I/O pads should be inserted for the desig- nated top-level module Design Methodologies - HDL Flow 5-7 ...
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... Click OK to synthesize the designated top-level design and its underlying modules. (Or, click Run to synthesis and implement the design.) The synthesis compiler automatically inserts top-level input and output pads required for implementation (unless instructed not the Synthesis Settings). Express Constraints Editor The Express Constraints Editor is available with the Foundation Express product only ...
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... The Clocks, Ports, and Paths tabs apply only to top-level HDL designs. 3. Right-click on an item in any of the spreadsheets to edit the value, access a dialog box to edit the value, or access a pulldown menu to select a value. Use the online help in the dialog boxes to under- stand and enter specific constraints and options. ...
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Foundation Series 2.1i User Guide Figure 5-3 Express Constraints Editor - Ports Tab 4. Optionally, you can import a constraints file (.exc) to use now (click Import Constraints) or you can export the entered constraints to a constraints file (.exc) ...
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... Synthesis Results. 2. Click the tabs to access the performance results in the various spreadsheets. If you unchecked Insert I/O pads on the Synthesis/Imple- mentation dialog, only the Models and Xilinx Options tabs are shown. The Clocks, Ports, and Paths tabs apply only to top-level HDL designs. ...
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Foundation Series 2.1i User Guide Figure 5-5 Express Time Tracker - Ports Tab Performing Functional Simulation Functional Simulation may be performed to verify that the logic you created is correct. Gate-level functional simulation is performed after the design is synthesized. ...
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Add signals by selecting Signal 4. From the Signals Selection portion of the Components Selection for Waveform Viewer window, select the signals that you want to see in the simulator. 5. Use CTRL-click to select multiple signals. Make sure ...
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Foundation Series 2.1i User Guide 8. In the Stimulator Selection window, create the waveform stimulus by attaching stimulus to the inputs. For more details on how to use the Stimulus Selection window, click Help. 9. After the stimulus has been ...
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Implementing the Design Design Implementation is the process of translating, mapping, placing, routing, and generating a Bit file for your design. Optionally, it can also generate post-implementation timing data. 1. Click the Implementation icon on the Implementation phase button on ...
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Foundation Series 2.1i User Guide Click OK to return to the Synthesis/Implementation Settings dialog box. 4. Click Options on the Synthesis/Implementation dialog box to set the Place and Route Effort level and edit implementation, simulation, or configuration options, if desired. ...
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... Applying constraints helps you to adapt your design’s performance to expected worst-case conditions. The user constraint file (.ucf ASCII file that holds timing and location constraints read (by NGDBuild) during the translate process in the Flow Engine and is combined with an EDIF or XNF netlist into an NGD file ...
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... Click the tabs to access the various spreadsheets. 3. Right-click on an item in any of the spreadsheets to access a dialog box to edit the value. Use the online help in the dialog boxes to understand and enter specific constraints and options. Or, refer to the online software document, Constraints Editor Guide for detailed information ...
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Figure 5-6 Implementation Constraints Editor - Ports Tab 4. After you finish editing the constraints, click Save to close the Constraints Editor window 5. You must rerun the Translate step in the Flow Engine to have your new constraints applied ...
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... For FPGAs, you can perform a post-MAP, post-place, or post- route timing analysis to obtain timing information at various stages of the design implementation. You can perform a post- implementation timing analysis on CPLDs after a design has been fitted. For details on how to use the Timing Analyzer, select Help ...
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If you have already saved test vectors (for instance, in the functional simulation), you may load these vectors into the timing simulator by selecting File Programming the ...
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... Select Next. 6. Define your ports in the Design Wizard-Ports window. Select Next the Design Wizards - Machines window, select the number of state machines that you want. Click Finish. The Wizard creates the ports and gives you a template in which you can enter your macro design. 8. ...
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ACTIONS process (clk) begin if clk’event and clk = ’1’ then end if; end process; -- signal assignment statements for combinatorial -- outputs out_c <= ’0’ when (Sreg0 = S2) else out_a <= ’1’ when ...
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Foundation Series 2.1i User Guide For more information about creating state machine modules, refer to the“State Machine Designs” chapter. Or, select Help Foundation Help Contents and then Click State Editor. HDL Designs with Instantiated Xilinx Unified Library Components It is ...
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... Synthesize the design by selecting the Synthesis button on the Project Manager Flow tab.The synthesizer will automatically include top level input and output pads for the designated top- level design. For more information about HDL designs, see the “HDL Design Entry and Synthesis” chapter or, in the HDL Editor window, select Help 3 ...
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... This section explains how to instantiate a LogiBLOX module into a VHDL design using Foundation. The example described below creates a RAM48X4S using LogiBLOX. 1. Access the LogiBLOX Module Selector window using one of the following methods. Its operation is the same regardless of where it is invoked. • • • ...
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In the LogiBLOX Module Selector window, define the type of LogiBLOX module and its attributes. The Module Name speci- fied here is used as the name of the instantiation in the VHDL code. Foundation Series 2.1i User Guide ...
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Foundation Series 2.1i User Guide 5. When you click OK, the LogiBLOX module is created automati- cally and added to the project library. The LogiBLOX module is a collection of several files including those listed below. The files are located ...
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In the HDL Editor, open the LogiBLOX-created .vhi file (memory.vhi) located under the current project. The .vhi file for the memory component created in the previous steps is shown below. ----------------------------------------------- -- LogiBLOX SYNC_RAM Module "memory" -- Created by ...
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Foundation Series 2.1i User Guide Cut and paste the Component Declaration from the LogiBLOX component’s .vhi file to your project’s VHDL code, placing it after the architecture statement in the VHDL code. Cut and past the Component Instantiation from the ...
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... This section explains how to instantiate a LogiBLOX module into a Verilog design using Foundation. The example described below creates a RAM48X4S using LogiBLOX. 1. Access the LogiBLOX Module Selector window using one of the following methods. Its operation is the same regardless of where it is invoked. • • • ...
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Foundation Series 2.1i User Guide • • the LogiBLOX Module Selector window, define the type of LogiBLOX module and its attributes. The Module Name speci- fied here is used as the name of the instantiation in the Verilog ...
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When you click OK, the LogiBLOX module is created automati- cally and added to the project library. The LogiBLOX module is a collection of several files including those listed below. The files are located in your Xilinx project directory ...
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Foundation Series 2.1i User Guide 6. In the HDL Editor, open the LogiBLOX- created .vei file (memory.vei) located under the current project. The .vei file for the memory component created in the previous steps is shown below. //--------------------------------------------------- // LogiBLOX ...
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Cut and paste the component instantiation from the .vei file into the design code. Give the added code an instance name and edit it to connect the ports to the signals. The Verilog design code with the LogiBLOX instantiation for ...
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... VHDL Instantiation This section explains how to instantiate a CORE component into a VHDL design using Foundation. 1. With a valid Foundation project open, access the CORE Generator window using one of the following methods. Its operation is the same regardless of where it is invoked. 5-36 STYLE = MAX_SPEED USE_RPM = FALSE Check Syntax in the HDL Editor ...
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Select Project dialog box, ensure that Design Entry is VHDL, that Behavioral Simulation is VHDL, and that the Vendor is Foundation. The Family entry should reflect the project’s target device. Click OK to exit the Project Options ...
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Foundation Series 2.1i User Guide 5. When the CORE’s window appears, enter a name for the compo- nent in the Component Name field. The name must begin with an alpha character. No extensions or uppercase letters are allowed. After the ...
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The customized CORE component is a collection of several files including those listed below. The files are located in your Xilinx project directory for the current project. component_name.coe component_name.xco component_name.edn component_name.vho component_name.mif The component name is the name given to ...
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Foundation Series 2.1i User Guide -- COMP_TAG_END ------ End COMPONENT Declaration ------------ -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- ...
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c_has_di => 1, c_en_polarity => 1, c_has_we => 1, c_has_rst => 1, c_address_width => 4, c_read_mif => 0, c_depth => 16, c_pipe_stages => 0, c_mem_init_radix => 16, c_default_data => "0", c_mem_init_file => "sram.mif", c_we_polarity => 1, c_generate_mif => 0); end ...
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Foundation Series 2.1i User Guide 9. In the HDL Editor, open the CORE’s .vho file (component_name.vho) located under the current project. 10. Open a second session of the HDL Editor. In the second HDL Editor window, open the VHDL file ...
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... With a valid Foundation project open, access the CORE Generator window using one of the following methods. Its operation is the same regardless of where it is invoked. • • 2. Select Project dialog box, ensure that Design Entry is Verilog, that Behavioral Simulation is Verilog, and that the Vendor is Foundation. The Family entry should reflect the project’ ...
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Foundation Series 2.1i User Guide 5. When the CORE’s window appears, enter a name for the compo- nent in the Component Name field. The name must begin with an alpha character. No extensions or uppercase letters are allowed. After the ...
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The component name is the name given to the CORE in the customization window. The port names are the names provided in the .veo file. An example .veo file produced by the CORE Generator system ...
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Foundation Series 2.1i User Guide // The following code must appear after the module in which instantiated. Ensure that the translate_off/_on compiler // directives are correct for your synthesis tool(s). //----------- Begin Cut here for ...
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MOD_TAG_END ------- End MODULE Declaration ------------- // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port ...
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... VHDL or Verilog design attach an XNF module in the VHDL or Verilog code, use the nets named in the PIN records and/or SIG records in the XNF file as the port names of the component instantiation. The following is an example XNF file with PIN and SIG records. SYM, current_state_reg<4>, DFF, LIBVER=2.0.0 PIN next_state< ...
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This designation allows the bus to be referenced in the VHDL component as a vector data type. 2. Using the filename of the XNF file as the name of the component and the name of nets in the XNF file ...
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Foundation Series 2.1i User Guide 1. From the Project Manager window, select File Libraries. 2. Select the target library for the desired device in the Attached Libraries window. 3. Click Add to add the library to your project. The library ...
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Document The file will be automatically added to the project when the entire design is analyzed later. Creating the Schematic and Generating a Netlist This section lists the basic steps for creating a schematic and gener- ating a ...
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... Note: If the HDL macros in the schematic have lower levels of hier- archy or use user-defined libraries, you must add the files for the lower levels to your project manually. Select Document the Project Manager to add the files. Foundation needs access to all the design files before synthesis can occur. Selecting a Netlist Format ...
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Click Run. Foundation links all the project files and synthesizes the design using the top-down methodology. HDL files from the schematic are added to the project when the sche- matic is analyzed. All HDL and State Machine files for ...
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Foundation Series 2.1i User Guide 5-54 Xilinx Development System ...
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HDL Design Entry and Synthesis This chapter give an overview of HDL file selection for projects, compares synthesis of HDL modules in Schematic Flow projects and HDL Flow projects, explains how to manage large designs, and discusses advanced design techniques. ...
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Foundation Series 2.1i User Guide • Create new document • • • Open • • 6-2 Use HDL Design Wizard Use this option for new designs. The Wizard includes dialogs for you to select the HDL language (VHDL or Verilog), ...
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Adding the File to the Project After creating an HDL file for an HDL Flow project, you must “add” the HDL file to the project. You can do this from within the HDL Editor by choosing Project can add files ...
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Foundation Series 2.1i User Guide Figure 6-1 VHDL Language Assistant Figure 6-2 Verilog Language Assistant 6-4 Xilinx Development System ...
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... Following is the general procedure to synthesize HDL Modules in Schematic Flow Projects. 1. Open the HDL file in the HDL Editor. This can be done by the methods listed in the “HDL File Selection” section or by double Foundation Series 2.1i User Guide HDL Design Entry and Synthesis 6-5 ...
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Foundation Series 2.1i User Guide clicking on the .vhd (VHDL (Verilog) file in the Project Manager. 2. Select Synthesis Options window. In the General tab, select the optimization options for the module. 3. Click on the Advanced tab. ...
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HDL Flow Methodology In an HDL Flow project, all top-level VHDL and Verilog files and schematics are exported to the synthesis tool and optimized. Pre- Implementation constraint editing, cross-boundary optimization, and auto I/O buffer insertion are only available in an ...
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Foundation Series 2.1i User Guide In the Synthesis Options dialog box, set the Default FSM Encoding style, XNF Bus Style, and Default Frequency. Check the Export Timing Constraint box if you want to have timing and pin location constraints entered ...
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... Express Constraints Editor before the design is optimized by the synthesis engine. Choose to view the estimated performance after optimization spreadsheets. This opens the Express Time Tracker and displays the design’s pre-implementation timing estimates. Click SET to access the Synthesis Setting and modify the ...
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... You need to select View Estimated Performance after Optimization in the Synthesis/Implemen- tation settings dialog box to view spreadsheets containing the results obtained as a result of setting the constraints. Refer to the“Using Constraints in an HDL Design” section for more information on constraints in HDL designs ...
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Instead, partition the design so that combinatorial paths are not split across multiple modules. This gives the software the best opportunity to optimize combinatorial logic on the path. A REG A Figure 6-4 Combinatorial Logic Path Split Across Boundaries (Inefficient ...
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... Editor. The Express Constraints Editor includes a window with five different tabs. The following three tabs represent constraints that can be applied to the design prior to synthesis: Clock, Paths, and Ports. • The Clocks tab allows you to specify overall speeds for the clocks in a design. 6-12 New Library from the Project Manger. ...
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... NCF file. Following is an example: TIMESPEC TS_CLK = PERIOD “CLK” HIGH 10; Currently, Express cannot apply all Xilinx constraints. Express can apply the following constraints: • PERIOD • FROM:TO timespecs which use FFS, LATCHES, and PADS • Pin location constraints • Slew rate • TNM_NET • ...
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Foundation Series 2.1i User Guide • TIG • user-RLOCs, RLOC_ORIGIN, RLOC_RANGE • non-I/O LOCs • KEEP • U_SET, H_SET, HU_SET • user-BLKNM and user-HBLKNM • PROHIBIT Express can create its own timegroups by grouping logic with common clocks and clock ...
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... EXT records correspond to pins used on a package. The EXT records named CLK, DATA, and SYNCFLG can be referenced in a pin locking constraint. For more information on Xilinx constraints, refer to the “Attributes, Constraints, and Carry Logic” chapter in the Libraries Guide. Reading Instance Names from an XNF file for UCF ...
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Foundation Series 2.1i User Guide Instance Names for LogiBLOX RAM/ROM In the Foundation Express methodology, whenever large blocks of RAM/ROM are needed, LogiBLOX RAM/ROM modules should be instantiated by the user in the HDL code. With LogiBLOX RAM/ ROM modules ...
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Each primitive in a LogiBLOX RAM/ROM module has an instance name of MEMx_y, where y represents the primitive position in the bank of memory, and where x represents the bit position of the RAM/ ROM output. Referencing LogiBLOX Entities This ...
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... Foundation Series 2.1i User Guide LogiBLOX RAM/ROM module. Consider the RAM32X2S example. Suppose that each of the RAM primitives needs to be constrained to a particular CLB location. Based on the rules for determining the MEMx_y instance names, using the example from above, each of the RAM primitives can be referenced by concatenating the full-hierarchical name to each of the MEMx_y names ...
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Figure 6-8 Verilog File with Instantiated LogiBLOX Module When the LogiBLOX module is created, a .vei file is created, which is used as an instantiation reference. Figure 6-9 VEI File Created by LogiBLOX Foundation Series 2.1i User Guide HDL Design ...
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Foundation Series 2.1i User Guide Figure 6-10 UCF File for Verilog Example Figure 6-11 Top-level VHDL Example File 6-20 Xilinx Development System ...
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Figure 6-12 VHDL File with Instantiated LogiBLOX Module Figure 6-13 VHI File Created By LogiBLOX Foundation Series 2.1i User Guide HDL Design Entry and Synthesis 6-21 ...
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Foundation Series 2.1i User Guide Figure 6-14 UCF File for VHDL Example 6-22 Xilinx Development System ...
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State Machine Designs This chapter explains the basic operations used to create state machine designs. State machine design typically starts with the translation of a concept into a “paper design,” usually in the form of a state diagram or a ...
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Foundation Series 2.1i User Guide “HDL Designs with State Machines” section of the “Design Methodologies - HDL Flow” chapter. State Machine Example The state machine in this example has four modes, which can be selected by two inputs: DIR (direction) ...
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Display = 5 Figure 7-1 State Diagram State Machine Implementation A state machine requires memory and the ability to make decisions. The actual hardware used to implement a state machine consists of state registers (flip-flops) and combinatorial logic (gates). State ...
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Foundation Series 2.1i User Guide Figure 7-2 Parts of a State Machine The amount of logic used to calculate the next state varies according to the type of state machine you are implementing. You must choose the most efficient design ...
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... An encoded state machine requires the same definition information as a symbolic machine, but in addition, it requires you to define the value of the state register for each state. Symbolic state machines are supported for CPLDs, but they are less efficient than encoded state machines. Compromises in State Machine Encoding ...
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... One-hot encoding reduces the width of the combinatorial logic and result, the state machine requires fewer levels of logic between registers, reducing its complexity and increasing its speed. Although one-hot encoding can be used for CPLDs and FPGAs better suited to FPGAs. One-Hot Encoding in Xilinx FPGA Architecture ...
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... Encoding for CPLDs CPLD devices generally implement binary-encoded state machines more efficiently. Binary encoding uses the minimum number of registers. Each state is represented by a binary number stored in the registers. Using as few registers as possible usually increases the amount of combinatorial logic needed to interpret each state. ...
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Foundation Series 2.1i User Guide 7-8 Xilinx Development System ...
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LogiBLOX LogiBLOX is an on-screen design tool for creating high-level modules such as counters, shift registers, and multiplexers for FPGA and CPLD designs. LogiBLOX includes both a library of generic modules and a set of tools for customizing these modules. ...
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Foundation Series 2.1i User Guide Setting Up LogiBLOX LogiBLOX is automatically installed with the Xilinx design imple- mentation tools and is ready to use from the Foundation Project Manager interface when you start the product. Starting LogiBLOX ...
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... You can use LogiBLOX components in schematics and HDL designs for FPGAs and CPLDs. Once you are in the LogiBLOX GUI, you can customize standard modules and process them for insertion into your design. Note: Once a LogiBLOX module is created, do not change parameters for the module on the schematic. Any changes to the module parameters must be made through the LogiBLOX GUI and a new module created ...
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Foundation Series 2.1i User Guide Figure 8-1 LogiBlox Module Selector - Accumulators Creating LogiBLOX Modules Once you have opened LogiBLOX, create a module as follows: 1. Enter the name of the module you want to create in the Module Name ...
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... The Project Manager automatically converts the EDIF netlist and reads the generic module file from the \fndtn\active\config\logi- blox directory and the MOD file to customize the module symbol. The Project Manager then generates the ALR and ASX files containing the module’s binary netlist and ports description and saves the module to the project working library ...
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Foundation Series 2.1i User Guide Using LogiBLOX for HDL Designs The tools for synthesis-based designs are described in the following subsections. Module-inferring Tools Base Express and Foundation Express infer LogiBLOX components where appropriate. Use the HDL Editor to create the ...
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CORE Generator System The Xilinx CORE Generator System is a design tool that delivers parameterizable COREs optimized for Xilinx FPGAs. It provides the user with a catalog of ready-made functions ranging in complexity frorm simple arithmetic operators such as adders, ...
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Foundation Series 2.1i User Guide Accessing the CORE Generator System In the Foundation Series 2.1i software, the CORE Generator System must be started within a valid Foundation project. Within an open project, it can be started from the Project Manager ...
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You can select Project setup options. However, the Foundation Series software automati- cally sets the Project Options (shown in the following figure) to the appropriate values for the project. You do not need to set them manu- ally. Foundation Series ...
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Foundation Series 2.1i User Guide You select a CORE by clicking on its name in the “Contents of” section of the CORE Generator window. This opens a new window where you can customize the CORE for your use, view its ...
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As shown in the figure below, the Language Assistant in the HDL Editor (Tools Modules. You can get assistance with instantiating them in VHDL or Verilog. Foundation Series 2.1i User Guide Language Assistant) includes CORE Generator CORE Generator System 9-5 ...
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Foundation Series 2.1i User Guide Instantiating CORE Generator Modules For information on using COREs in schematic designs, refer to the “Schematic Designs With Instantiated CORE Generator Cores” section of the “Design Methodologies - Schematic Flow” chapter. For information on using ...
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Functional Simulation For schematic and HDL designs, functional simulation is performed before design implementation to verify that the logic you created is correct. Your design methodology determines when you perform functional simulation. Generally, for Schematic Flow projects, you can perform ...
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Foundation Series 2.1i User Guide Note: For a schematic design, you can invoke the simulator (for functional simulation) from the Schematic Editor by clicking on the Simulator toolbar button. Attaching Probes (Schematic Editor Only) Prior to opening the Simulator, you ...