HW-SPAR3-SK-UNI-G Xilinx Inc, HW-SPAR3-SK-UNI-G Datasheet - Page 28

• Manufacturer Part Number: HW-SPAR3-SK-UNI-G
• Description: KIT STARTER SPARTAN-3
• Manufacturer: Xilinx Inc
• Series: Spartan-3r
• Type: FPGA Configurationr

Specifications of HW-SPAR3-SK-UNI-G

• Contents: Board, Cable, Software, Datasheets and User Manual
• For Use With/related Products: Spartan-3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1521

Keyboard
28
R
bidirectional keyboard communications. As shown in
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
Table 6-2: PS/2 Bus Timing
The following site contains additional information on the PS/2 bus protocol:
•
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends a “F0” key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different “shift” and “non-shift” characters and regardless whether the Shift key is pressed
or not. The host determines which character is intended.
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,
they may send more than one scan code. When an extended key is released, a “E0 F0” key-
up code is sent, followed by the scan code.
PS/2 Mouse/Keyboard Protocol
http://www.computer-engineering.org/ps2protocol/
Symbol
T
T
T
6-3.
HLD
CK
SU
DATA (PS2D)
CLK (PS2C)
Clock High or Low time
Data-to-clock setup time
Clock-to-data hold time
Figure 6-2: PS/2 Bus Timing Waveforms
www.xilinx.com
Edge 0
T
Parameter
SU
'0' start bit
Spartan-3 FPGA Starter Kit Board User Guide
T
T
CK
HLD
Chapter 6: PS/2 Mouse/Keyboard Port
T
Figure
CK
'1' stop bit
6-2, the attached keyboard or
UG130_c6_02_042404
UG130 (v1.2) June 20, 2008
Edge 10
30 μs
Min
5 μs
5 μs
50 μs
25 μs
25 μs
Max