HW-MP-TQ144 Xilinx Inc, HW-MP-TQ144 Datasheet - Page 7

• Manufacturer Part Number: HW-MP-TQ144
• Description: ADAPTER 144-TQFP COOLRUNNER II
• Manufacturer: Xilinx Inc

Specifications of HW-MP-TQ144

• Accessory Type: Programming Adapter
• For Use With/related Products: XC2C128 144-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 3
Table 3: Mating Connectors for 2 mm pitch, 14 Conductor Ribbon Cable
Table 4
Table 4: Mating Connectors for 2 mm pitch, 34 Conductor Ribbon Cable
Interface Pin Descriptions
The interface pins for the Serial/JTAG/SPI, SelectMAP, and adapter ports are described in
respectively.
Table 5: SS/JTAG/SPI Port: 14-Pin Ribbon Cable Connector
DS114 (v1.9) February 8, 2008
Product Specification
Notes:
1.
2.
3.
Notes: Also available in surface mount or without keyed shroud.
Comm Con
OUPIIN
Comm Con
OUPIIN
Number
Ribbon
Cable
10
12
14
Also available in surface mount or without keyed shroud.
Some manufacturer’s pin assignments do not conform to Xilinx pin assignments.
Please refer to the manufacturer's data sheet for more information.
Additional 14-pin ribbon cables can be purchased separately from the
2
4
6
8
lists some third-party sources for mating connectors for 2 mm pitch, 14-conductor ribbon cable.
lists third-party sources for mating connectors for 2 mm pitch, 34-conductor ribbon cable.
Configuration
Slave-Serial
R
Manufacturer
Manufacturer
PROG
DONE
Mode
CCLK
V
INIT
DIN
N/C
REF
Configuration
JTAG
Mode
V
N/C
N/C
REF
–
–
–
–
Programming
Mode
SPI
V
N/C
N/C
REF
–
–
–
–
(2)
3112-14G00SBA/SN
3112-34G00SBA/SN
Part Number
Part Number
2422-14G2
2422-34G2
www.xilinx.com
BIDIR
Type
Out
Out
Out
Out
In
In
Xilinx Online
Target Reference Voltage.
voltage bus on the target system that serves the JTAG, slave-serial
interface. or SPI. For example, when programming a Coolrunner-II
device using the JTAG port, V
V
Configuration Reset. This pin is used to force a reconfiguration of
the target FPGA(s). It should be connected to the PROG_B pin of the
target FPGA for a single-device system, or to the PROG_B pin of all
FPGAs in parallel in a daisy-chain configuration.
Configuration Clock. FPGAs load one configuration bit per CCLK
cycle in slave-serial mode. CCLK should be connected to the CCLK
pin on the target FPGA for a single-device configuration, or to the
CCLK pin of all FPGAs in parallel in a daisy-chain configuration.
Configuration Done. This pin indicates to MultiPRO tool that target
FPGAs have received the entire configuration bitstream. It should be
connected to the Done pin on all FPGAs in parallel for daisy-chained
configurations. Additional CCLK cycles are issued following the positive
transition of Done to insure that the configuration process is complete.
Configuration Data Input. This is the serial input data stream for
target FPGAs. It should be connected to the DIN pin of the target
FPGA in a single-device system, or to the DIN pin of the first FPGA
in a daisy-chain configuration.
Test Driver. This pin is reserved for Xilinx diagnostics and should not
be connected to any target circuitry.
Configuration Initialize. This pin indicates that configuration
memory is being cleared. It should be connected to the INIT_B pin of
the target FPGA for a single-device system, or to the INIT_B pin on
all FPGAs in parallel in a daisy-chain configuration.
AUX
bus.
Store.
Description
(3)
REF
This pin should be connected to a
Table
should be connected to the target
5,
MultiPRO Desktop Tool
Table
6, and
Table
7,
7