HW-MP-TQ144 Xilinx Inc, HW-MP-TQ144 Datasheet - Page 8

• Manufacturer Part Number: HW-MP-TQ144
• Description: ADAPTER 144-TQFP COOLRUNNER II
• Manufacturer: Xilinx Inc

Specifications of HW-MP-TQ144

• Accessory Type: Programming Adapter
• For Use With/related Products: XC2C128 144-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5: SS/JTAG/SPI Port: 14-Pin Ribbon Cable Connector (Cont’d)
Table 6: SelectMAP Port: 34-Pin Ribbon Cable Connector Interface Pin Descriptions
DS114 (v1.9) February 8, 2008
Product Specification
Notes:
1.
2.
3.
1, 3, 5, 7,
9, 11, 13
Number
Ribbon Cable Pin
Ribbon
Cable
10
10
All odd pins (1, 3, 5, 7, 9, 11, and 13) should be connected to digital ground on the target end of the ribbon cable. Minimum crosstalk is
achieved when using all grounds.
The listed SPI pin names match those of SPI flash memories from STMicroelectronics. Pin names of compatible SPI devices from other
vendors can be different. Consult the vendor's SPI device data sheet for corresponding pin names.
Caution! The PROG_B pin of the FPGA, which is connected to a target SPI device, must be asserted Low during SPI programming to
ensure the FPGA does not contend with the SPI programming operation.
The target reference voltage must be regulated and must not have a current-limiting resistor in series with the V
4
6
8
4
6
8
Number
16
14
12
10
18
20
22
24
26
8
6
4
2
Configuration
Slave-Serial
R
Mode
–
–
–
–
–
–
–
–
–
Configuration Mode
Configuration
SelectMAP
RDWR
DONE
CCLK
BUSY
JTAG
Mode
TMS
TDO
INIT
TCK
TDI
D0
D1
D2
D3
D4
D5
D6
D7
–
–
–
–
–
Programming
Mode
SPI
MISO
MOSI
SCK
SS
–
–
–
–
–
(2)
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
Type
OUT
OUT
IN
IN
www.xilinx.com
Type
Out
Out
Out
Out
Out
Out
In
In
–
Byte-Wide Data Bus, Bit 0
Byte-Wide Data Bus, Bit 1
Byte-Wide Data Bus, Bit 2
Byte-Wide Data Bus, Bit 3
Byte-Wide Data Bus, Bit 4
Byte-Wide Data Bus, Bit 5
Byte-Wide Data Bus, Bit 6
Byte-Wide Data Bus, Bit 7
Configuration Clock
Configuration Read / Write Control
Configuration Flow Control
Configuration Done
Configuration Initialize
Test Mode Select. This is the JTAG mode signal that establishes
appropriate TAP state transitions for target ISP devices. It should be
connected to the TMS pin on all target ISP devices that share the
same data stream.
Test Clock. This is the clock signal for JTAG operations, and should
be connected to the TCK pin on all target ISP devices that share the
same data stream.
Test Data Out. This is the serial data stream received from the TDO
pin on the last device in a JTAG chain.
Test Data In. This is the serial data stream transmitted to the TDI pin
on the first device in a JTAG chain.
SPI Select. This pin is the active-Low SPI chip select signal. This
should be connected to the S
SPI Clock. This pin is the clock signal for SPI operations and should
be connected to the C
SPI Master-Input, Slave-Output. This pin is the target serial output
data stream for SPI operations and should be connected to the Q
pin on the SPI flash PROM.
SPI Master-Output Slave-Input. This pin is the target serial input
data stream for SPI operations and should be connected to the D
pin on the SPI flash PROM.
Digital Ground.
(1)
(2)
pin on the SPI flash PROM.
Description
Description
(2)
pin on the SPI flash PROM.
MultiPRO Desktop Tool
REF
pin.
(2)
(2)
8