EM35X-DEV-UPG-IAR Ember, EM35X-DEV-UPG-IAR Datasheet - Page 160
EM35X-DEV-UPG-IAR
Manufacturer Part Number
EM35X-DEV-UPG-IAR
Description
IAR EWARM LICENCE FOR EM35X
Manufacturer
Ember
Type
Licenser
Specifications of EM35X-DEV-UPG-IAR
For Use With/related Products
EM35x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1028
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TIMx_EGR
TIM1_EGR
Timer 1 Event Generation Register
TIM2_EGR
Timer 2 Event Generation Register
Bitname
TIM_TG
TIM_CC4G
TIM_CC3G
TIM_CC2G
TIM_CC1G
TIM_UG
31
23
15
7
0
0
0
0
TIM_TG
30
22
14
0
0
0
6
Bitfield
[6]
[4]
[3]
[2]
[1]
[0]
29
21
13
0
0
0
5
0
Access
W
W
W
W
W
W
Description
Trigger Generation.
0: Does nothing.
1: Sets the TIM_TIF flag in the INT_TIMxFLAG register.
Capture/Compare 4 Generation.
0: Does nothing.
1: If CC4 configured as output channel:
The TIM_CC4IF flag is set.
If CC4 configured as input channel:
The TIM_CC4IF flag is set.
The INT_TIMMISSCC4IF flag is set if the TIM_CC4IF flag was already high.
The current value of the counter is captured in TMRx_CCR4 register.
Capture/Compare 3 Generation.
0: Does nothing.
1: If CC3 configured as output channel:
The TIM_CC3IF flag is set.
If CC3 configured as input channel:
The TIM_CC3IF flag is set.
The INT_TIMMISSCC3IF flag is set if the TIM_CC3IF flag was already high.
The current value of the counter is captured in TMRx_CCR3 register.
Capture/Compare 2 Generation.
0: Does nothing.
1: If CC2 configured as output channel:
The TIM_CC2IF flag is set.
If CC2 configured as input channel:
The TIM_CC2IF flag is set.
The INT_TIMMISSCC2IF flag is set if the TIM_CC2IF flag was already high.
The current value of the counter is captured in TMRx_CCR2 register.
Capture/Compare 1 Generation.
0: Does nothing.
1: If CC1 configured as output channel:
The TIM_CC1IF flag is set.
If CC1 configured as input channel:
The TIM_CC1IF flag is set.
The INT_TIMMISSCC1IF flag is set if the TIM_CC1IF flag was already high.
The current value of the counter is captured in TMRx_CCR1 register.
Update Generation.
0: Does nothing.
1: Re-initializes the counter and generates an update of the registers. This also clears the
prescaler counter but the prescaler ratio is not affected. The counter is cleared if center-
aligned mode is selected or if TIM_DIR=0 (up-counting), otherwise it takes the auto-reload
value (TMR1_ARR) if TIM_DIR=1 (down-counting).
TIM_CC4G
28
20
12
4
0
0
0
Final
9-36
TIM_CC3G
27
19
11
0
0
0
3
TIM_CC2G
26
18
10
2
0
0
0
Address: 0x4000F014 Reset: 0x0
Address: 0x4000E014 Reset: 0x0
TIM_CC1G
25
17
0
0
9
0
1
120-035X-000G
TIM_UG
24
16
0
0
8
0
0
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