ICL7104-14CPL Intersil, ICL7104-14CPL Datasheet - Page 15

• Manufacturer Part Number: ICL7104-14CPL
• Description: 14 BIT A/D CONVERTER
• Manufacturer: Intersil

Specifications of ICL7104-14CPL

• Rohs Status: RoHS non-compliant
• Other names: NT5018

the SEN input will be high when the handshake mode is
entered after new data is stored. The CE/LD and HBEN ter-
minals will go low after SEN is sensed, and the high order
byte outputs become active. When CE/LD goes high at the
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UART TBRE
output will now go low, which halts the output cycle with the
HBEN output low, and the high order byte outputs active.
When the UART has transferred the data to the Transmitter
Register and cleared the Transmitter Buffer Register, the
TBRE returns high. On the next ICL7104 internal clock high
to low edge, the high order byte outputs are disabled, and
one-half internal clock later, the HBEN output returns high.
At the same time, the CE/LD and MBEN (-16) or LBEN out-
puts go low, and the corresponding byte outputs become
active. Similarly, when the CE/LD returns high at the end of
one clock period, the enabled data is clocked into the UART
Transmitter Buffer Register, and TBRE again goes low.
When TBRE returns to a high it will be sensed on the next
ICL7104 internal clock high to low edge, disabling the data
outputs. For the 16-bit device, the sequence is repeated for
INTEGRATOR OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
INTERNAL MODE
HIGH BYTE DATA
STATUS OUTPUT
LOW BYTE DATA
LOW BYTE DATA
MODE INPUT
SEN INPUT
CE/LOAD
HBEN
LBEN
LBEN
UART
NORM
MODE HIGH ACTIVATES
CE/LD, HBEN, LBEN
DON’T CARE
FIGURE 11. HANDSHAKE WITH SEN HELD POSITIVE
ZERO-CROSSING OCCURS
ZERO-CROSSING DETECTED
SENSED
SEN
DATA VALID
THREE-STATE HIGH IMPEDANCE
ICL7104
15
LBEN. One-half internal clock later, the handshake mode will
be cleared, and the chip and byte ENABLE terminals return
high and stay active (as long as MODE stays high).
With the MODE input remaining high as in these examples,
the converter will output the results of every conversion
except those completed during a handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure 13 shows a
handshake output sequence triggered by such an edge. In
addition, the SEN input is shown as being low when the con-
verter enters handshake mode. In this case, the whole out-
put sequence is controlled by the SEN input, and the
sequence for the first (high order) byte is similar to the
sequence for the other bytes. This diagram also shows the
output sequence taking longer than a conversion cycle. Note
that the converter still makes conversions, with the STATUS
output and Run/Hold input functioning normally. The only
difference is that new data will not be latched when in
handshake mode, and is therefore lost.
DISABLES OUTPUTS CE/LD, HBEN, MBEN, LBEN
DATA VALID
MODE LOW NOT IN HANDSHAKE MODE
FOR -16 MBEN SEQUENCE INSERTED HERE
SENSED
SEN
DATA VALID
THREE-STATE WITH PULLUP
TERMINATES
UART MODE