cat34c02 Catalyst Semiconductor, cat34c02 Datasheet

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cat34c02

Manufacturer Part Number
cat34c02
Description
2-kb I?c Eeprom For Ddr2 Dimm Serial Presence Detect
Manufacturer
Catalyst Semiconductor
Datasheet

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CAT34C02
2-Kb I
FEATURES
PIN FUNCTIONS
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PIN CONFIGURATION
A
SDA
SCL
WP
V
V
For Ordering Information details, see page 15.
0
CC
SS
Supports Standard and Fast I
1.7 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Software Write Protection for lower 128 Bytes
Schmitt Triggers and Noise Suppression Filters
on I
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
RoHS-compliant packages
Industrial temperature range
, A
1
, A
2
2
C Bus Inputs (SCL and SDA).
C EEPROM for DDR2 DIMM Serial Presence Detect
2
For the location of Pin 1, please consult the
corresponding package drawing.
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
V SS
A 0
A 1
A 2
UDFN (HU3)
TDFN (VP2)
TSSOP (Y)
1
2
3
4
8
7
6
5
V CC
WP
SCL
SDA
2
C Protocol
1
* Catalyst carries the I
DEVICE DESCRIPTION
The CAT34C02 is a 2-Kb Serial CMOS EEPROM,
internally organized as 16 pages of 16 bytes each, for
a total of 256 bytes of 8 bits each.
It features a 16-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory) or by setting an
internal Write Protect flag via Software command (this
protects the lower half of the memory).
In addition to Permanent Software Write Protection,
the CAT34C02 also features JEDEC compatible
Reversible Software Write Protection for DDR2 Serial
Presence Detect (SPD) applications operating over
the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with
earlier DDR1 SPD applications operating over the
1.7 V to 5.5 V supply voltage range.
FUNCTIONAL SYMBOL
2
C protocol.
A 2 , A 1 , A 0
SCL
WP
2
C protocol under a license from the Philips Corporation.
CAT34C02
V CC
V SS
Doc. No. MD-1095, Rev. K
SD A

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cat34c02 Summary of contents

Page 1

... Characteristics subject to change without notice DEVICE DESCRIPTION 2 C Protocol The CAT34C02 is a 2-Kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) ...

Page 2

... CAT34C02 (1) ABSOLUTE MAXIMUM RATINGS Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground RELIABILITY CHARACTERISTICS Symbol Parameter (4) N Endurance END T Data Retention DR D.C. OPERATING CHARACTERISTICS -40°C to +85°C, unless otherwise specified Symbol Parameter I Supply Current (Read Mode) ...

Page 3

... ( θ , where the Junction Temperature Example: CAT34C02VP2 3 ( θ , where the Case Temperature, etc © Catalyst Semiconductor, Inc. Characteristics subject to change without notice ...

Page 4

... POWER-ON RESET (POR) The CAT34C02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT34C02 will power up into Standby mode after V exceeds the POR trigger level and will power CC down into Reset mode when V ...

Page 5

... Catalyst Semiconductor, Inc. Characteristics subject to change without notice DEVICE ADDRESS 8 ACK DELAY (≤ HIGH LOW t LOW t HD:DAT t SU:DAT CAT34C02 STOP BIT R/W BUS RELEASE DELAY (RECEIVER) 9 ACK SETUP (≥ t SU:DAT ) t SU:STO t BUF Doc No. MD-1095, Rev. K ...

Page 6

... The internal Write cycle starts immediately following the STOP. Acknowledge Polling Acknowledge polling can be used to determine if the CAT34C02 is busy writing or is ready to accept com- mands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS). ...

Page 7

... R ADDRESS ADDRESS ACK t WR STOP CONDITION BYTE ADDRESS (n) DATA SU:WP t HD:WP 7 CAT34C02 DATA START ADDRESS CONDITION DATA n+1 DATA n DATA Doc No. MD-1095, Rev. K ...

Page 8

... Sequential Read st If the Master acknowledges the 1 data byte transmitted by the CAT34C02, then the device will continue trans- mitting as long as each data byte is acknowledged by the Master (Figure 11). If the end of memory is reached during sequential Read, then the address counter will ‘wrap-around’to the beginning of memory, etc. Sequential Read works with either ‘ ...

Page 9

... Bit DATA OUT NO ACK SLAVE BYTE R ADDRESS ADDRESS (n) ADDRESS DATA n DATA n+1 DATA n CAT34C02 STOP S T SLAVE DATA DATA n ...

Page 10

... The state of the WP pin is strobed on the last falling to set, edge of SCL immediately preceding the first data byte 0 (Figure 8). If the WP pin is HIGH during the strobe inter- val, the CAT34C02 will not acknowledge the data byte and the Write request will be rejected. FFH 7FH condition must be ...

Page 11

... R ADDRESS ADDRESS Don't Care BUS ACTIVITY: SLAVE R MASTER ADDRESS T SDA LINE CAT34C02 ACK Address ACK Data ACK ? Byte ? Byte ? Yes X Yes X Yes 0 Yes X Yes Yes Yes ...

Page 12

... CAT34C02 PACKAGE DIMENSIONS TSSOP 8-Lead 4.4mm ( TOP VIEW SIDE VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC specification MO-153. Doc. No. MD-1095, Rev. K ...

Page 13

... All dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC specification MO-229. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice SIDE VIEW MAX A2 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 13 CAT34C02 PACKAGE OUTLINE DRAWING e b PIN#1 IDENTIFICATION D2 L BOTTOM VIEW A3 FRONT VIEW Doc. No. TDFN8-008-01 08/24/07 Doc No. MD-1095, Rev. K ...

Page 14

... CAT34C02 UDFN 8-Pad 2 x 3mm (HU3) UDFN 8-Pad 2 x 3mm (HU3 PIN #1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.45 0.50 A1 0.00 0.02 A3 0.127 REF b 0.20 0.25 D 1.90 2.00 D2 1.50 1.60 E 2.90 3.00 E2 0.10 0.20 e 0.50 TYP K 0.10 REF L 0.30 0.35 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. ...

Page 15

... All packages are RoHS-compliant (Lead-free, Halogen-free) (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT34C02YI-GT5 (TSSOP, Industrial Temperature, NiPdAu, 5000 pcs / Reel) (4) The TDFN and UDFN packages are available in 4000 pcs/Reel (i.e., CAT34C02VP2I-GT4, CAT34C02HU3I-GT4). (5) The TSSOP (Y) package (i.e., CAT34C02YI-GT5) is available in 5000 pcs / Reel. ...

Page 16

... CAT34C02 REVISION HISTORY Date Revision Comments 09/27/05 A Initial Issue 09/28/05 B Update Features Update Absolute Maximum Ratings Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update A.C. Characteristics 2 Update I C Bus Protocol - Power-On Reset (POR) 10/03/05 C Update Power-On Reset (POR) 11/05/05 D Update Ordering Information Add Tape and Reel Specifications ...

Page 17

... Information” or “Preliminary” and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 17 CAT34C02 Doc No. MD-1095, Rev. K ...

Page 18

... Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: MD-1095 Revison: K Issue date: 01/17/08 ...

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