ds90c363 National Semiconductor Corporation, ds90c363 Datasheet

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ds90c363

Manufacturer Part Number
ds90c363
Description
+3.3v Programmable Lvds Transmitter 18-bit Flat Panel Display Fpd Link?65 Mhz, +3.3v Lvds Receiver 18-bit Flat Panel Display Fpd Link?65 Mhz
Manufacturer
National Semiconductor Corporation
Datasheet

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© 1999 National Semiconductor Corporation
DS90C363/DS90CF364
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver
18-Bit Flat Panel Display (FPD) Link— 65 MHz
General Description
The DS90C363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data through-
puts is 170 Mbytes/sec. The Transmitter is offered with pro-
grammable edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be pro-
grammed for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will inter-
operate with a Falling edge Receiver (DS90CF364) without
any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS012886
Application
Features
n 20 to 65 MHz shift clock support
n Programmable Transmitter (DS90C363) strobe select
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption
n Power-down mode (
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 170 Megabyte/sec bandwidth
n Up to 1.3 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating
n Operating Temperature: −40˚C to +85˚C
(Rising or Falling edge strobe)
>
7 kV
<
0.5 mW total)
<
DS012886-14
September 1999
250 mW (typ)
www.national.com

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ds90c363 Summary of contents

Page 1

... Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link— 65 MHz General Description The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted ...

Page 2

... Block Diagrams (Continued) www.national.com DS90C363 DS012886-1 Order Number DS90C363MTD See NS Package Number MTD48 DS90CF364 DS012886-24 Order Number DS90CF364MTD See NS Package Number MTD48 2 ...

Page 3

... Differential Input Low Threshold TL I Input Current IN TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current, Worst Case ICCTG Transmitter Supply Current, 16 Grayscale (Note 1) DS90C363 DS90CF364 Package Derating: DS90C363 DS90CF364 −0.3V to +4V ESD Rating + 0.3V) CC (HBM, 1 100 pF) + 0.3V 0.3V) Recommended Operating CC + 0.3V) CC Conditions Continuous +150˚C ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTZ Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current, Worst Case ICCRG Receiver Supply Current, 16 Grayscale ICCRZ Receiver ...

Page 5

Transmitter Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol Parameter LLHT LVDS Low-to-High Transition Time (Figure 3 ) LVDS High-to-Low Transition Time (Figure 3 ) LHLT TCIT TxCLK IN Transition Time (Figure 5 ...

Page 6

Receiver Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol CLHT CMOS/TTL Low-to-High Transition Time (Figure 4 ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) CHLT RSPos0 Receiver Input Strobe Position for Bit 0 ...

Page 7

... Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 9: Recommended pin to signal mapping. Customer may choose to define differently. FIGURE 3. DS90C363 (Transmitter) LVDS Output Load and Transition Times FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time ...

Page 8

... TxCLK Differential Low High Edge FIGURE 6. DS90C363 (Transmitter) Channel-to-Channel Skew FIGURE 7. DS90C363 (Transmitter) Setup/Hold and High/Low Times FIGURE 8. DS90CF364 (Receiver) Setup/Hold and High/Low Times FIGURE 9. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) www.national.com DS012886-17 DS012886-18 DS012886-5 DS012886-19 ...

Page 9

... AC Timing Diagrams (Continued) FIGURE 10. DS90CF364 (Receiver) Clock In to Clock Out Delay FIGURE 11. DS90C363 (Transmitter) Phase Lock Loop Set Time FIGURE 12. DS90CF364 (Receiver) Phase Lock Loop Set Time DS012886-6 DS012886-20 DS012886-7 9 www.national.com ...

Page 10

AC Timing Diagrams (Continued) FIGURE 13. Seven Bits of LVDS in One Clock Cycle FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com FIGURE 15. Transmitter Power Down Delay FIGURE 16. Receiver Power Down Delay 10 DS012886-9 ...

Page 11

AC Timing Diagrams (Continued) FIGURE 17. Transmitter LVDS Output Pulse Position Measurement 11 DS012886-22 www.national.com ...

Page 12

AC Timing Diagrams (Continued) FIGURE 18. Receiver LVDS Input Strobe Position www.national.com 12 DS012886-25 ...

Page 13

... Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 MHz. Note 11: ISI is dependent on interconnect length; may be zero. FIGURE 19. Receiver LVDS Input Skew Margin DS90C363 Pin Description — FPD Link Transmitter Pin Name I/O No. ...

Page 14

... OR left unconnected. When not connected (left open) and internal pull-down resistor ties pin 14 to ground, thus configuring the trans- mitter with a falling edge strobe. 3. The DS90C363 transmitter input and control inputs ac- cept 3.3V TTL/CMOS levels. They are not 5V tolerant. www.national.com Description ...

Page 15

... Pin Diagram DS90C363 Pin R_FB R_FB DS90CF364 DS012886-23 TABLE 1. Programmable Transmitter Condition Strobe Status R_FB = V Rising edge strobe CC R_FB = GND Falling edge strobe 15 DS012886-13 www.national.com ...

Page 16

... Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C363MTD and DS90CF364MTD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION ...

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