DS90CR218 National Semiconductor, DS90CR218 Datasheet
DS90CR218
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DS90CR218 Summary of contents
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... LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR218 receiver converts the three LVDS data streams back into 21 bits of CMOS/TTL data transmit clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel ...
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... Pin Diagram Typical Application www.national.com 10087122 DS90CR218 2 10087123 ...
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... Note 2: Typical values are given for V = 3.3V and T CC Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except V and (Note 1) Package Derating DS90CR218 ESD Rating (HBM, 1.5k , 100pF) −0.3V to +4V (EIAJ 200pF) + 0.3V) Latch Up Tolerance CC + 0.3V 0.3V) ...
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... Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218/288 receiver is TCCD Timing Diagrams FIGURE 2. DS90CR218 (Receiver) CMOS/TTL Output Load and Transition Times www.national.com Parameter ...
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... AC Timing Diagrams (Continued) FIGURE 3. DS90CR218 (Receiver) Setup/Hold and High/Low Times FIGURE 4. DS90CR218 (Receiver) Clock In to Clock Out Delay FIGURE 5. DS9OCR218 (Receiver) Phase Lock Loop Set Time 10087110 10087112 10087114 5 www.national.com ...
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AC Timing Diagrams FIGURE 6. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR217) www.national.com (Continued) FIGURE 7. Receiver Powerdown Delay 6 10087116 10087118 ...
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AC Timing Diagrams (Continued) FIGURE 8. Receiver LVDS Input Strobe Position 7 10087128 www.national.com ...
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... Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 6: Cycle-to-cycle jitter is less than 250 ps at 75MHz Note 7: ISI is dependent on interconnect length; may be zero FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR217/DS90CR218) DS90CR218 Pin Description—Channel Link Receiver Pin Name I/O No ...
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... Applications Information The DS90CR217 and DS90CR218 are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR213, DS90CR214). To upgrade from 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the V , LVDS V and PLL Transmitter input and control inputs except 3.3V TTL/ CMOS levels ...
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Applications Information DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ce- ramic type in surface mount form factor) between each V and ...
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Applications Information The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) Order Number DS90CR218MTD Dimensions in millimeters only NS Package Number MTD48 2 ...