IDT82V3012PV IDT, Integrated Device Technology Inc, IDT82V3012PV Datasheet
IDT82V3012PV
Specifications of IDT82V3012PV
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IDT82V3012PV Summary of contents
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FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks • Supports ITU-T G.812 Type IV clocks • Supports ETSI ETS 300 011, ...
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IDT82V3012 DESCRIPTION The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked kHz, ...
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Pin Description...................................................................................................................................................................................................7 2 Functional Description ....................................................................................................................................................................................10 2.1 State Control Circuit ................................................................................................................................................................................10 2.1.1 Normal Mode..............................................................................................................................................................................11 2.1.2 Fast Lock Mode..........................................................................................................................................................................11 2.1.3 Holdover Mode ...........................................................................................................................................................................11 2.1.4 Freerun Mode.............................................................................................................................................................................11 2.2 Frequency Select Circuit .........................................................................................................................................................................11 2.3 Reference Input Switch ...........................................................................................................................................................................11 2.4 Reference Input Monitor ...
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MHz Input to 19.44 MHz Output Jitter Transfer.............................................................................................................................24 7.10 8 kHz Input Jitter Tolerance.....................................................................................................................................................................24 7.11 1.544 MHz Input Jitter Tolerance ............................................................................................................................................................24 7.12 2.048 MHz Input Jitter Tolerance ............................................................................................................................................................25 7.13 19.44 MHz Input Jitter Tolerance ............................................................................................................................................................25 8 Timing Characteristics ...
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Figure - 1 IDT82V3012 SSOP56 Package Pin Assignment ................................................................................................................................ 2 Figure - 2 State Control Circuit .......................................................................................................................................................................... 10 Figure - 3 State Control Diagram....................................................................................................................................................................... 10 Figure - 4 TIE Control Block Diagram................................................................................................................................................................ 12 Figure - 5 Reference Switch with TIE ...
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Table - 1 Operating Modes Selection ................................................................................................................................................................10 Table - 2 Fref0 Frequency Selection .................................................................................................................................................................11 Table - 3 Fref1 Frequency Selection .................................................................................................................................................................11 Table - 4 Input Reference Selection ..................................................................................................................................................................12 Table - 5 C2/C1.5 Output Frequency Control....................................................................................................................................................15 List of Tables LIST OF ...
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IDT82V3012 1 PIN DESCRIPTION Name Type Pin Number 12, 18 Power SS 38 Power 37, 48 DDA V Power 13, 19, 26 DDD OSCi (CMOS Fref0 5 I Fref1 6 IN_sel I 11 F0_sel0 ...
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IDT82V3012 Name Type Pin Number C19POS 21 (LVDS) O C19NEG 22 C19o (CMOS C32o (CMOS C16o (CMOS C8o (CMOS C4o (CMOS C2o (CMOS C3o (CMOS C1.5o ...
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IDT82V3012 Name Type Pin Number IC0, IC2 - 53, 55 Pin Description T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS These pins should be connected Description February 6, 2009 ...
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IDT82V3012 2 FUNCTIONAL DESCRIPTION The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs, providing timing (clock) and synchronization (framing) signals to interface circuits for multitrunk T1/E1 and STS3/OC3 links. The details are described in the following sections. 2.1 ...
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IDT82V3012 The mode changes between Normal (S1) and Auto-Holdover (S2) are triggered by the Invalid Input Reference Detection Circuit and are irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At the stage of S1, if the input ...
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IDT82V3012 Table - 4. The selected reference signal is sent to the TIE control block, Reference Input Monitor and Invalid Input Signal Detection block for further processing. Table - 4 Input Reference Selection IN_sel 0 1 When a transient voltage ...
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IDT82V3012 Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s Figure - 5 Reference Switch ...
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IDT82V3012 Fraction_C19 Fraction_T1 Fraction_C6 Loop Filter Limiter FLOCK In the Normal mode, the Limiter receives the error signal from the Phase Detector, limits the phase slope within 5 ns per 125 µs and sends the limited signal to the Loop ...
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IDT82V3012 The 32.768 MHz signal is used by the E1_divider to generate five types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal 50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o, RSP and ...
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IDT82V3012 IDT82V3012 RST Rp 1 kΩ Figure - 9 Power-Up Reset Circuit 2.11 POWER SUPPLY FILTERING TECHNIQUES To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources of ...
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IDT82V3012 3 MEASURES OF MANCE The following are some synchronizer performance indicators and their corresponding definitions. 3.1 INTRINSIC JITTER Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output measured by applying ...
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IDT82V3012 3.11 PHASE CONTINUITY Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of ...
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IDT82V3012 4 ABSOLUTE MAXIMUM RATINGS Ratings Power supply voltage Voltage on any pin with respect to ground Package power dissipation Storage temperature Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This ...
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IDT82V3012 6.2 DIFFERENTIAL OUTPUT PORT (LVDS) Parameter Description VOD Differential Output Voltage Change in Magnitude of VOD for ∆ VOD Complementary Output States VOS Offset Voltage Change in Magnitude of VOS for ∆ VOS Complementary Output States VOH Output Voltage ...
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IDT82V3012 7 AC ELECTRICAL CHARACTERISTICS 7.1 PERFORMANCE Description Freerun Mode accuracy with OSCi at: 0 ppm Freerun Mode accuracy with OSCi at: ±32 ppm Freerun Mode accuracy with OSCi at: ±100 ppm Holdover Mode accuracy with OSCi at: 0 ppm ...
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IDT82V3012 7.2 INTRINSIC JITTER UNFILTERED Description Intrinsic jitter at F8o (8 kHz) Intrinsic jitter at F0o (8 kHz) Intrinsic jitter at F16o (8 kHz) Intrinsic jitter at C1.5o (1.544 MHz) Intrinsic jitter at C3o (3.088 MHz) Intrinsic jitter at C2o ...
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IDT82V3012 7.6 8 KHZ INPUT TO 8 KHZ OUTPUT JITTER TRANSFER Description Jitter attenuation for 1 Hz@0.01 UIpp input Jitter attenuation for 1 Hz@0.54 UIpp input Jitter attenuation for 10 Hz@0.10 UIpp input Jitter attenuation for 60 Hz@0.10 UIpp input ...
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IDT82V3012 7.9 19.44 MHZ INPUT TO 19.44 MHZ OUTPUT JITTER TRANSFER Description Jitter attenuation for 1 Hz@20 UIpp input Jitter attenuation for 1 Hz@104 UIpp input Jitter attenuation for 10 Hz@20 UIpp input Jitter attenuation for 60 Hz@20 UIpp input ...
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IDT82V3012 7.12 2.048 MHZ INPUT JITTER TOLERANCE Description Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input Jitter tolerance ...
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IDT82V3012 Notes: Voltages are with respect to ground (V ) unless otherwise stated. Supply voltage and SS operating temperature are as per Recommended Operating Conditions. Timing parameters are as per Timing Parameter Measurement Voltage Levels. 1. Fref0 reference input selected. ...
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IDT82V3012 8 TIMING CHARACTERISTICS 8.1 TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS Parameter V Threshold Voltage T V Rise and Fall Threshold Voltage High HM V Rise and Fall Threshold Voltage Low LM All Siganls t IRF, Notes: 1. Voltages are with ...
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IDT82V3012 Parameter Description t F8o to C19o delay C19D t F8o to C32o delay C32D t F8o to TSP delay TSPD t F8o to RSP delay RSPD t C1.5o pulse width high or low C15W t C3o pulse width high ...
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IDT82V3012 Fref0/Fref1 8 kHz Fref0/Fref1 1.544 MHz Fref0/Fref1 2.048 MHz Fref0/Fref1 19.44 MHz F8o Timing Characteristics T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS R15D R2D Figure - 12 Input to ...
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IDT82V3012 F8o F0o F16o F32o C32o C16o C8o t C4W C4o C2o (see Note 1) C6o C3o C1.5o (see Note 1) F19o C19o C19POS C19NEG Timing Characteristics T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS t F0WL t F16WL t F16S ...
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IDT82V3012 F8o C2o RSP TSP Note 1: The timing characteristic of C2/C1.5 (2.048 MHz or 1.544 MHz) is the same as that of C2o or C1.5o. F8o MODE_sel0 MODE_sel1 TIE_en IN_sel Timing Characteristics T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS ...
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IDT82V3012 9 ORDERING INFORMATION XXXXXXX Device Type Package DATASHEET DOCUMENT HISTORY 07/21/2003 pgs 10/22/2003 pgs. 1, 10, 11, 19, 20, 25, 26 02/02/2004 pgs. 14, 15 11/18/2004 pgs. 1, 10, 31 05/24/2006 pgs 02/06/2009 ...