M29W400DT55N6 NUMONYX, M29W400DT55N6 Datasheet

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... Top device code M29W400DT: 00EEh – Bottom device code M29W400DB: 00EFh ® – ECOPACK packages August 2007 4 Mbit (512 256 Kb x 16, boot block) 1. These packages are no more in mass production. Rev 5 M29W400DT M29W400DB 3 V supply Flash memory (1) SO44 (M) TSOP48 ( FBGA (1) TFBGA48 (ZA FBGA TFBGA48 (ZE) ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M29W400DT, M29W400DB 4.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 ...

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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M29W400DT, M29W400DB List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Description 1 Description The M29W400D Mbit (512 256 Kb x 16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. ...

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M29W400DT, M29W400DB Figure 1. Logic diagram Table 1. Signal names Signal name A0-A17 DQ0-DQ7 DQ8-DQ14 DQ15A– BYTE A0-A17 W M29W400DT E M29W400DB Function ...

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Description Figure 2. SO connections Not connected. 8/ A17 ...

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M29W400DT, M29W400DB Figure 3. TSOP connections Not connected. A15 1 48 A14 A13 A12 A11 A10 M29W400DT M29W400DB A17 ...

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Description Figure 4. TFBGA connections (top view through package Not connected. 10/ A17 ...

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M29W400DT, M29W400DB Figure 5. Block addresses (x 8) M29W400DT Top boot block addresses (x 8) 7FFFFh 16 Kbyte 7C000h 7BFFFh 8 Kbyte 7A000h 79FFFh 8 Kbyte 78000h 77FFFh 32 Kbyte 70000h 6FFFFh 64 Kbyte 60000h 1FFFFh 64 Kbyte 10000h 0FFFFh ...

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Description Figure 6. Block addresses (x 16) M29W400DT Top boot block addresses (x 16) 3FFFFh 8 Kword 3E000h 3DFFFh 4 Kword 3D000h 3CFFFh 4 Kword 3C000h 3BFFFh 16 Kword 38000h 37FFFh 32 Kword 30000h 0FFFFh 32 Kword 08000h 07FFFh 32 ...

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... Figure 1: Logic this device. 2.1 Address inputs (A0-A17) The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation ...

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... PHPHH 2.9 Ready/Busy output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance ...

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... This prevents Bus Write operations from accidentally damaging the data LKO during power-up, power-down and power surges. If the Program/Erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 µF capacitor should be connected between the V ground pin to decouple the current surges from the power supply ...

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... Enable are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the command interface. A valid Bus Read operation involves setting the desired address on the Address inputs, applying a Low signal, V ...

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... They require V applied to some pins. 3.7 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and Table 3, Bus operations ...

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Bus operations Table 3. Bus operations, BYTE = V Operation Bus Read Bus Write Output Disable Standby Read manufacturer code Read device code 18/48 IH Address inputs A0-A17 ...

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... Data inputs/outputs DQ0-DQ7, otherwise 00h is output. 4.3 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data and starts the Program/Erase controller. ...

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... Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory ...

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... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks ...

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... Command interface will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued not possible to select any further blocks to erase after the Erase Resume ...

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M29W400DT, M29W400DB Table 5. Commands, 16-bit mode, BYTE = V Command 1st Addr 1 X Read/Reset 3 555 Auto Select 3 555 Program 4 555 Unlock Bypass 3 555 Unlock Bypass 2 X Program Unlock Bypass 2 X Reset Chip ...

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... DQ7, not its complement. During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling bit will change from a ’ ...

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... Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’ ...

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Status Register Table 7. Status Register bits Operation Block Erase before timeout Block Erase Erase Suspend Erase Error 1. Unspecified data bits should be ignored. Figure 7. Data polling flowchart 26/48 (1) (continued) Address DQ7 DQ6 Erasing block 0 Toggle ...

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M29W400DT, M29W400DB Figure 8. Data toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C Status Register 27/48 ...

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Maximum rating 6 Maximum rating Stressing the device above the rating listed in cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of ...

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M29W400DT, M29W400DB 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under ...

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DC and AC parameters Table 10. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 11. DC characteristics Symbol I Input Leakage current LI I Output Leakage current LO I Supply ...

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M29W400DT, M29W400DB Table 12. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ( Chip Enable Low to Output Transition ELQX LZ t ...

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DC and AC parameters Figure 12. Write AC waveforms, Write Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 13. Write AC characteristics, Write Enable controlled Symbol Alt t t Address Valid to Next Address ...

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M29W400DT, M29W400DB Figure 13. Write AC waveforms, Chip Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 14. Write AC characteristics, Chip Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...

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DC and AC parameters Figure 14. Reset/Block Temporary Unprotect AC waveforms tPLPX RP Table 15. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL ...

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M29W400DT, M29W400DB 8 Package mechanical Figure 15. SO44 - 44 lead plastic small outline, 525 mils body width, package outline b 1. Drawing is not to scale. Table 16. SO44 – 44 lead plastic small outline, 525 mils body width, ...

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Package mechanical Figure 16. TSOP48 – 48 lead plastic thin small outline mm, package outline DIE 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead plastic thin small outline ...

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M29W400DT, M29W400DB Figure 17. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline 1. Drawing is not to scale. Table 18. TFBGA48 mm active ball ...

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Package mechanical Figure 18. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline 1. Drawing is not to scale. Table 19. TFBGA48 mm active ball ...

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... E = ECOPACK package, standard packing F = ECOPACK package, Tape & Reel packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...

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Block address table Appendix A Block address table Table 21. Top boot block addresses M29W400DT # Size (Kbytes ...

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... Section 2: Signal Unlike the command interface of the Program/Erase controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another. ...

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Block protection Table 23. Programmer technique bus operations, BYTE = V Operation Block Protect Chip Unprotect Block Protection Verify Block Unprotection Verify 42/48 Address inputs A12-A17 block address ...

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M29W400DT, M29W400DB Figure 19. Programmer equipment block protect flowchart START ADDRESS = BLOCK ADDRESS Wait 4 µ Wait 100 ...

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Block protection Figure 20. Programmer equipment chip unprotect flowchart NO 44/48 START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4 µ ...

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M29W400DT, M29W400DB Figure 21. In-system equipment block protect flowchart START WRITE 60h ADDRESS = BLOCK ADDRESS WRITE 60h ADDRESS ...

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Block protection Figure 22. In-system equipment chip unprotect flowchart 46/48 START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...

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M29W400DT, M29W400DB 10 Revision history Table 24. Document revision history Date Revision 26-Jul-2002 19-Feb-2003 28-May-2003 30-Sep-2003 6-Oct-2003 16-Jan-2004 8-Jun-2004 07-Aug-2007 01 Initial release Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and ...

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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...