x3101 Intersil Corporation, x3101 Datasheet
x3101
Related parts for x3101
x3101 Summary of contents
Page 1
... A/D converter to achieve better resolution than a more expensive 14-bit converter. An internal 4k-bit EEPROM memory featuring IDLock allows the designer to partition and “lock in” written battery cell/pack data. The X3100 and X3101 are each housed TSSOP package. Functional Diagram VCELL1 CB1 ...
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... ON/OFF. 3 VCELL2 Battery cell 2 voltage. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. 2 X3100, X3101 X3100, X3101 (28 LD TSSOP) ...
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... CB3 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. 7 VCELL4/ Battery cell 4 voltage (X3100) Ground (X3101). This pin is used to monitor the voltage of this battery cell internally. The VSS voltage of an individual cell can also be monitored externally at pin AO. ...
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... This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is possible when OVP/LMON=V X3101 turn off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the application of charging voltage for an extended period of time (see section “Over-charge Protection” on page 14). ...
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... Power to the X3100 or X3101 is applied to pin VCC via diodes D6 and D7. These diodes allow the device to be powered by the Li-Ion battery cells in normal operating conditions, and allow the device to be powered by an external source (such as a charger) via pin P+ when the battery cells are being charged. These diodes should have sufficient current and voltage ratings to handle both cases of battery cell charge and discharge ...
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... Initial connection of the Li-Ion cells in the battery pack will not normally power-up the battery pack. Instead, the X3100 or X3101 enters and remains in the SLEEP mode. To exit the SLEEP mode, after the initial power-up sequence, or following any other SLEEP MODE, a minimum of 16V ...
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... Typical Application Circuit 7 X3100, X3101 FN8110.1 January 3, 2008 ...
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... SIGNAL) OCDS STATUS REGISTER BIT 0 VRGS+OCDS STATUS REGISTER BIT 2 (SWCEN = 0) CCES+OVDS STATUS REGISTER BIT 2 (SWCEN = 1) OVDS AS2_AS0 SPI PORT 8 X3100, X3101 T PUR 5V ±10% (STABLE AND REPEATABLE) V TUNED TO 5V ±0.5% RGO 2ms (Typ X3100/1 in Overcurrent Protection Mode 0 = X3100/1 NOT in Overcurrent Protection Mode ...
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... Configuration Register The X3100 and X3101 can be configured for specific user requirements using the Configuration Register. TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY BIT(s) NAME – (don’t care) 6 SWCEN Switch Cell Charge Enable threshold function ON/OFF 7 CELLN Set the number of Li-ion battery cells ...
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... EEPROM into the SRAM configuration regis- ter upon power-up (Figure 1 the case that the X3100 or X3101 is configured for use with only three Li-Ion battery cells (i.e. CELLN = 0), then VCELL4 (pin 7) MUST be tied to Vss (pin 9) to ensure correct operation. ...
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... Write 12 Enable 13 14 Write to 15 4kbit EEPROM Sleep Control (SLP) Power-down Setting the SLP bit to ‘1’ forces the X3100 or X3101 Power-up into the sleep mode Mode” on page 16. Table 13. Sleep Mode Selection Control Register Bits OVPC CSG1 CSG0 ...
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... CB1 - CB4 can be controlled by using the WCNTR In- struction to set bits CBC1 - CBC4 in the control register (Table 16). STATUS REGISTER The status of the X3100 or X3101 can be verified by using the RDSTAT command to read the contents of the Status Register (Table 17). Table 17. Status Register The function of each bit in the status register is shown Operation in Table 18 ...
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... Cell Charge Enable CELL Voltage (V ). Over-charge Voltage Detection Status CE (OVDS internally generated signal which indi- cates whether or not the X3100 or X3101 is in over- charge protection mode. Table 18. Status Register Functionality. Bit(s) Name Description 0 VRGS+OCDS Voltage regulator ...
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... Over-charge Protection The X3100 and X3101 monitor the voltage on each battery cell ( for any cell, V CELL time exceeding T , then the Charge FET will be OV switched OFF (OVP/LMON = V CC now entered Over-charge protection mode (Figure 3). The status of the discharge FET (via pin UVP) will remain unaffected ...
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... UVP/OCP or OVP/LMON using the control register) [3] — All cell voltages fall below V — The X3100/X3101 automatically switches charge FET = ON (OVP/LMON = Vss) — The status of the discharge FET remains unaffected. — Charging of the battery cells can now resume. ...
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... The device returns from sleep mode when V (e.g. when the battery terminals are connected to a battery charger). In this case, the X3100 or the X3101 restores the 5VDC regulated output (section “Voltage Regulator” on page 22), and communication via the SPI port resumes. ...
Page 17
... At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 22). (2,3) — The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA. — The output of the 5VDC voltage regulator (RGO) is 0V. — Access to the X3100/X3101 via the SPI port is NOT possible. 17 X3100, X3101 0.7V ...
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... The internal over-discharge release timer times out, AND V — The device returns from over-discharge protection mode, and is now in normal operation mode. — The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep. — The discharge FET is can now be switched ON (UVP/OCP = V the UVPC bit of the control register. — ...
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... X3100, X3101 If the load resistance > R exceeding T from over-current protection mode. The discharge FET is then automatically switched ON (UVP/OCP = Vss) by the X3100 or X3101, unless the status of UVP/OCP has been changed in control register (by manipulating bit UVPC) during the over-current protection mode. FET OFF ...
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... It is possible to change the status of UVPC and OVPC in the control register, although the status of pins UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection mode. (2,3) — The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over- current condition is still present across the battery terminals P+/P-. 20 ...
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... VCS2 - VCS Notes: (1) This is the normal state of the X3100 or X3101. While in this state Over-charge and Over-discharge Protec- tion conditions are periodically monitored (See “Peri- odic Protection Monitoring” on page 13.) (2) VCS , VCS are read at AO with respect bias ...
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... The internal gain of the X3100 or X3101 current sense voltage amplifier can be selected by using the WCNTR Instruction to set bits CSG1 and CSG0 in the control register (Table 14). The CSG1 and CSG0 bits select one of four input resistors to Op Amp OP1. The feed- back resistors remain constant. This ratio of input to feedback resistors determines the gain ...
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... The SI pin carries the input signal and SO provides the output signal. SCK clocks data in or out. The X3100 and X3101 operate in SPI mode 0 which requires SCK to be normally low when not transferring data. It also specifies that the rising edge of SCK clocks data into the device, while the falling edge of SCK clocks data out ...
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... Table 30. X3100/X3101 Instruction Set Instruction Instruction Name Format* WREN 0000 0110 WRDI 0000 0100 EEWRITE 0000 0010 EEREAD STAT 0000 0101 EEREAD 0000 0011 WCFIG 0000 1001 WCNTR 0000 1010 RDSTAT 0000 1011 SET IDL 0000 0001 *Instructions have the MSB in leftmost position and are transferred MSB first. ...
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... This is minimally a thirty-two clock opera- tion. CS must go LOW and remain LOW for the dura- tion of the operation. The host may continue to write bytes of data to the X3100 or X3101. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “ ...
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... SI Figure 12. EEPROM Read Status (EEREAD STAT) Operation Sequence SCK EEREAD STAT Instruction SI Nonvolatile EEWRITE in Progress SO 26 X3100, X3101 Byte Address (2 Byte Data Byte 3 ...
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... When reading from the X3100 or X3101 EEPROM memory first pulled LOW to select the device. The 8-bit EEREAD instruction is transmitted to the X3100 or X3101, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be zeroes). After the EEREAD opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line ...
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... SI High Impedance SO Control Bits 28 X3100, X3101 Write Control Register (WCNTRL) The Write Control Register (WCNTRL) instruction updates the contents of the volatile Control Register. This command sets the status of the FET control pins, the cell balancing outputs, the current sense gain and external entry to the sleep mode. Since this ...
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... X3100, X3101 Set ID Lock (SET IDL) The contents of the EEPROM memory array in the X3100 or X3101 can be locked in one of eight configu- rations using the SET ID lock command. When a sec- tion of the EEPROM array is locked, the contents cannot be changed, even when a valid write operation attempts a write to that area ...
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... OVP/LMON, CB1-CB4) VOL3 Output LOW voltage (RGC) VOH3 Output HIGH voltage (RGC) Note: (1) V min. and V max. are for reference only and are not 100% tested X3100, X3101 Parameter Max. Supply Voltage +70°C X3100/X3101 Limits Min. Max. ±10 ± ...
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... Cell over-charge detection time Cell over-discharge protection mode (SLEEP) threshold. (Default in Boldface) Cell over-discharge protection mode release threshold Cell over-discharge detection time Cell over-discharge release time 31 X3100, X3101 Sym Condition V On power- wake-up RGO After self-tuning (@10mA V current; 25 RGO ...
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... For reference only, this parameter is not 100% tested. Wake-up test circuit (X3100) Vcc Vcc RGP VCELL1 RGC VCELL2 RGO VCELL3 VCELL4 Vss Increase Vcc until V 32 X3100, X3101 Sym Condition ( 0.075V (VOC1, VOC0 = 0, 0.100V (VOC1, VOC0 = 0, 0.125V (VOC1, VOC0 = 1,0) ...
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... OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage 5VDC voltage regulator current limit V supply current ( supply current ( supply current ( supply current ( supply current (5) CC Cell over-charge protection mode voltage threshold (Default in Boldface) ...
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... V = 0.5V (Vce1, Vce0 = 0, 0.8V (Vce1, Vce0 = 0, 1.1V (Vce1, Vce0 = 1, 1.4V (Vce1, Vce0 = 1, See Wake-up test circuit SLR V See Sleep test circuit SLP Sleep test circuit (X3101) V RGO turns on (2) Min Typ 0.050 0.100 0.060 0.090 0.075 0.125 ...
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... Input capacitance (SCK, SI, CS) IN Notes: (8) This parameter is not 100% tested. Equivalent A.C. Load Circuit 5V 2061Ω SO 30pF 3025Ω 35 X3100, X3101 Parameter is stable until a read or write can be initiated. These parameters are RGO Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level Min ...
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... CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile WC write cycle. Serial Input Timing CS t LEAD SCK MSB X3100, X3101 Voltage Min. Max. Units 0 3.3 MHz 300 ns ...
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... SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A 37 X3100, X3101 Voltage t t CYC MSB–1 Out OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH ...
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... Change in Current Sense Gain Amplification and Control Bits C S SCK DI OVPC CSG1 CSG0 Control Reg Bit10 Bit9 Bit8 AO Old Gain Current Sense Gain Change UVP/OCP OVP/LMON On CB4:CB1 RGC Control Off Outputs 38 X3100, X3101 Parameter 0 0 SLP x Bit7 Bit6 Bit5 t CSGO t CO Min. Typ. Max. Units 1.0 ms 1.0 ms 1.0 µs ...
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... TYPICAL OPERATING CHARACTERISTICS Norm al Operating Current 150 125 100 75 50 -20 25 Tem perature X3100/X3101 Over Charge Trip Voltage (Typical) 4.40 4.35 4.30 4.25 4.20 4.15 -25 25 Temperature (Deg C) 4.2V Setting 4.3V Setting X3101 Over Discharge Trip Voltage (Typical) 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 -25 25 Temperature (Deg C) 2.25V Setting 2.45V Setting For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143 ...
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... X3100, X3101 40 FN8110.1 January 3, 2008 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 41 X3100, X3101 M28.173 M B ...