x40626 Intersil Corporation, x40626 Datasheet
x40626
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x40626 Summary of contents
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... Reset logic V CC REV 1.1.15 2/11/04 X40626 DESCRIPTION The X40626 combines four popular functions, Power-on Reset Control, Watchdog Timer, Dual Supply Voltage CC Supervision, and Serial EEPROM Memory in one pack- age. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time ...
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... X40626 operating level and stabilizes. Four industry standard Vtrip thresholds are available. However, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’ ...
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... X40626 PRINCIPLES OF OPERATION Power On Reset Application of power to the X40626 activates a Power On Reset Circuit that pulls the RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...
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... V address is 0FH TRIP2 for V address is 03H TRIP X40626 www.xicor.com voltage start by setting the WEL TRIP pin and the programming the WP pin and 2 byte address and 1 P programming sequence. Bring WP TRIP ...
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... X40626 Figure 4. V Programming Sequence TRIP New V applied = X Old V applied + | Error | X Error < MDE REV 1.1.15 2/11/04 V Programming TRIPX Desired No V TRIPX Present Value YES Set V = Desired V X TRIPX Execute Set Higher V Sequence TRIPX Execute Set Higher V Sequence X Apply V and Voltage CC > Desired ...
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... The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X40626 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation ...
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... X40626 not block protected can be written. Note that since the WPEN bit is write protected, it cannot be changed back Table 1. Write Protect Enable Bit and WP Pin Function Memory Array not WP WPEN Block Protected LOW X Writes OK HIGH 0 Writes OK HIGH 1 Writes OK Writing to the Control Register ...
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... X40626 Figure 5. Valid Data Changes on the SDA Bus SCL SDA Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met ...
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... X40626 Figure 7. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After ...
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... X40626 Figure 9. Page Write Operation S T Signals from Slave A the Master Address SDA Bus 1 Signals from the Slave Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around). 8 Bytes address = 7 The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle ...
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... X40626 Figure 11. Acknowledge Polling Sequence Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK returned? YES Nonvolatile Cycle complete. Continue command sequence? YES Continue Normal Read or Write Command Sequence PROCEED Figure 12. Current Address Read Sequence ...
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... X40626 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes ...
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... Signals from the Slave X40626 Addressing Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: – a device type identifier that is ‘1010’ to access the array – one bit of ‘0’. ...
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... X40626 Figure 15. X40626 Addressing Device Identifier 1 A15 A7 D7 Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possible to write to the device. – SDA pin is in the input mode. ...
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... X40626 ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to VSS ....-1.0V to +7V D.C. output current (sink).................................... 10mA Lead temperature (soldering, 10 seconds).........300°C Table 2. Recommended Operating Conditions Temp Min. Commercial 0°C Industrial -40° ...
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... X40626 CAPACITANCE (T = 25° 1.0 MHz Symbol (4) C Output Capacitance (SDA, RESET, V2FAIL) OUT (4) C Input Capacitance (SCL, WP, S0, S1) IN Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V 1533Ω SDA RESET 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) ...
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... X40626 TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing SCL SDA IN WP Write Cycle Timing SCL 8th bit of Last Byte SDA Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Notes: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
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... X40626 Power-Up and Power-Down Timing V /V TRIP TRIP2 V /V2MON CC 0 Volts t R RESET/V2FAIL RESET Output Timing Symbol t Power-up Reset Timeout PURST ( Detect to Reset/Output (Falling Edge) RPD CC ( /V2MON Fall Time /V2MON Rise Time R CC (8) V Reset Valid V ...
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... X40626 RESET Output Timing Symbol Parameter t Watchdog Timeout Period, WDO WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 t Reset Timeout RST V Programming Timing Diagram (WEL = 1) TRIP V /V2MON TRIP TRIP2 t TSU WP t VPS SCL SDA Start REV 1 ...
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... X40626 Packaging Information 14-Lead Plastic Small Outline Gullwing Package Type S Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° – 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.15 2/11/04 0.150 (3.80) 0.158 (4.00) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) X 45° ...
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... X40626 PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.15 2/11/04 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .019 (.50) .029 (.75) Detail A (20X) www.xicor.com .252 (6.4) BSC .041 (1.05) .010 (.25) ...
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... SOIC 0°C–70°C -40°C–85°C 14L TSSOP 0°C–70°C -40°C–85°C 14-Lead SOIC/TSSOP X40626 SOIC V = TSSOP YYWWXX XX – Part Mark WW – Workweek YY – Year www.xicor.com Part Number RESET Park ...
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... X40626 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...