PIC18F44J50-I/ML Microchip Technology, PIC18F44J50-I/ML Datasheet - Page 328
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F44J50-I/ML
Manufacturer Part Number
PIC18F44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
4.PIC18F24J50-ISS.pdf
(18 pages)
5.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18LF24J50-ISS PDF datasheet #2
- PIC18LF24J50-ISS PDF datasheet #3
- PIC18F24J50-ISS PDF datasheet #4
- PIC18F26J11-ISO PDF datasheet #5
- Current page: 328 of 554
- Download datasheet (9Mb)
PIC18F46J50 FAMILY
FIGURE 19-4:
FIGURE 19-5:
TABLE 19-5:
DS39931C-page 328
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
ODCON2
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1:
Note:
(Interrupt Reg. Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREGx
(Transmit Buffer
Reg. Empty Flag)
Name
Write to TXREGx
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
BRG Output
(Shift Clock)
TRMT bit
TXx (pin)
TXxIF bit
TRMT bit
TXx (pin)
TXxIF bit
This timing diagram shows two consecutive transmissions.
These bits are only available on 44-pin devices.
EUSARTx Transmit Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PMPIE
PMPIP
ABDOVF
PMPIF
SSP2IF
SSP2IE
SSP2IP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
—
1 T
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
(1)
(1)
(1)
CY
Word 1
Transmit Shift Reg
Transmit Shift Reg.
Word 1
Word 1
Word 1
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
—
1 T
CY
Start bit
Start bit
Word 2
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
—
1 T
CY
bit 0
bit 0
TXDTP
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
—
bit 1
Word 1
bit 1
Word 1
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
RBIE
Bit 3
CTMUIF
CTMUIE TMR3GIE
CTMUIP TMR3GIP
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
bit 7/8
bit 7/8
TMR3GIF
Word 2
Transmit Shift Reg.
TMR2IE
TMR2IP
TMR2IF
Stop bit
INT0IF
OERR
TRMT
U2OD
© 2009 Microchip Technology Inc.
WUE
Bit 1
Stop bit
Start bit
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
TMR1IF
ABDEN
U1OD
RX9D
TX9D
RBIF
Bit 0
Word 2
on Page:
Values
bit 0
Reset
63
65
65
65
65
65
65
65
65
65
66
65
65
68
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