PIC18F44J50-I/ML Microchip Technology, PIC18F44J50-I/ML Datasheet - Page 333
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F44J50-I/ML
Manufacturer Part Number
PIC18F44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
4.PIC18F24J50-ISS.pdf
(18 pages)
5.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18LF24J50-ISS PDF datasheet #2
- PIC18LF24J50-ISS PDF datasheet #3
- PIC18F24J50-ISS PDF datasheet #4
- PIC18F26J11-ISO PDF datasheet #5
- Current page: 333 of 554
- Download datasheet (9Mb)
19.3
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTAx<4>). In addition, enable bit, SPEN
(RCSTAx<7>), is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CKx line. Clock polarity is
selected with the TXCKP bit (BAUDCONx<4>). Setting
TXCKP sets the Idle state on CKx as high, while clear-
ing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module.
19.3.1
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
FIGURE 19-11:
© 2009 Microchip Technology Inc.
RC7/RX1/DT1/
SDO1/RP18
RC6/TX1/CK1/RP17 pin
(TXCKP = 0)
RC6/TX1/CK1/RP17 pin
(TXCKP = 1)
Write to
TXREG1 Reg
TX1IF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to
EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
EUSART Synchronous Master
Mode
EUSART SYNCHRONOUS MASTER
TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘1’
Write Word 1
SYNCHRONOUS TRANSMISSION
bit 0
Write Word 2
bit 1
Word 1
bit 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PIC18F46J50 FAMILY
Once the TXREGx register transfers the data to the
TSR register (occurs in one T
and the TXxIF flag bit is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF is set regardless of the state
of enable bit, TXxIE; it cannot be cleared in software. It
will reset only when new data is loaded into the
TXREGx register.
While flag bit, TXxIF, indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit, so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
bit 7
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the required baud
rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is required, set bit, TX9.
Enable the transmission by setting bit, TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
bit 0
Word 2
bit 1
CY
), the TXREGx is empty
DS39931C-page 333
bit 7
‘1’
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