PIC16F88-I/SO Microchip Technology, PIC16F88-I/SO Datasheet - Page 112

• Manufacturer Part Number: PIC16F88-I/SO
• Description: IC MCU FLASH 4KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 7
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
11.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RB2/SDO/RX/DT pin on the falling
edge of the clock. If enable bit SREN is set, then only a
single word is received. If enable bit CREN is set, the
reception is continuous until CREN is cleared. If both
bits are set, CREN takes precedence.
After clocking the last bit, the received data in the
Receive Shift Register (RSR) is transferred to the
RCREG register (if it is empty). When the transfer is
complete, interrupt flag bit, RCIF (PIR1<5>), is set. The
actual interrupt can be enabled/disabled by setting/
clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read-only bit which is reset by the
hardware. In this case, it is reset when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It is
possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register. On the clocking of the last
bit of the third byte, if the RCREG register is still full, then
Overrun Error bit, OERR (RCSTA<1>), is set. The word
in the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essential to clear bit OERR if it is set.
The ninth receive bit is buffered the same way as the
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
DS30487C-page 110
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
by
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
AUSART SYNCHRONOUS MASTER
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
setting
AUSART Receive Data Register
Baud Rate Generator Register
CSRC
SPEN
Bit 7
GIE
—
—
either
ADIE
ADIF
PEIE
Bit 6
RX9
TX9
enable
(1)
(1)
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
Bit 5
bit
SREN
CREN
SYNC
Bit 4
TXIF
TXIE
ADDEN
SSPIF
SSPIE
RBIE
Bit 3
—
receive data. Reading the RCREG register will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCSTA register, before reading
RCREG, in order not to lose the old RX9D information.
When setting up a synchronous master reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that GIE and PEIE
TMR0IF
CCP1IF TMR2IF TMR1IF -000 0000
CCP1IE TMR2IE TMR1IE -000 0000
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1 “AUSART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if enable bit, RCIE, was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
(bits 7 and 6) of the INTCON register are set.
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
 2005 Microchip Technology Inc.
0000 000x
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on:
0000 000u
-000 0000
0000 000x
0000 0000
-000 0000
0000 -010
0000 0000
Value on
all other
Resets