PIC16F88-I/SO Microchip Technology, PIC16F88-I/SO Datasheet - Page 114

• Manufacturer Part Number: PIC16F88-I/SO
• Description: IC MCU FLASH 4KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 7
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
11.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS30487C-page 112
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
AUSART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
AUSART Receive Data Register
Baud Rate Generator Register
SPEN
CSRC
Bit 7
GIE
—
—
ADIF
ADIE
PEIE
Bit 6
RX9
TX9
(1)
(1)
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
ADDEN
SSPIE
SSPIF
RBIE
Bit 3
—
When setting up a synchronous slave reception, follow
these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IF
BRGH
FERR
Bit 2
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TMR2IF TMR1IF -000 0000 -000 0000
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
Bit 0
RBIF
 2005 Microchip Technology Inc.
0000 000x 0000 000u
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on:
Value on
all other
Resets