PIC18LF2420-I/ML Microchip Technology, PIC18LF2420-I/ML Datasheet - Page 130

• Manufacturer Part Number: PIC18LF2420-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2420-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
12.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1:
FIGURE 12-2:
DS39631E-page 128
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Timer1 Operation
T1OSI
T1OSI
T1OSCEN
Timer1 Oscillator
T1CKPS<1:0>
T1SYNC
TMR1ON
Timer1 Oscillator
T1OSCEN
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1CKPS<1:0>
T1SYNC
TMR1ON
(1)
(1)
TMR1CS
TMR1CS
(CCP Special Event Trigger)
(CCP Special Event Trigger)
Clear TMR1
Clear TMR1
Clock
Internal
F
Clock
Internal
F
OSC
OSC
/4
/4
On/Off
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Prescaler
1, 2, 4, 8
Prescaler
1, 2, 4, 8
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
2
OSC
TMR1L
TMR1L
/4). When the bit is set, Timer1 increments
8
Sleep Input
Synchronize
Sleep Input
8
Synchronize
Detect
Detect
High Byte
High Byte
TMR1H
TMR1
TMR1
8
© 2008 Microchip Technology Inc.
8
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
on Overflow
on Overflow
TMR1IF
TMR1IF
Set
Set
Timer1
On/Off
Timer1
On/Off