PIC24FJ256GA106-I/PT Microchip Technology, PIC24FJ256GA106-I/PT Datasheet
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PIC24FJ256GA106-I/PT Summary of contents
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... PIC24FJ256GA110 Family General Purpose Flash Microcontrollers © 2008 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit with Peripheral Pin Select Preliminary DS39905B ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - available pins (100-pin devices) • ...
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... Selectable write protection boundary - Write protection option for Flash Configuration Words PIC24FJXXXGA106 Preliminary SOSCO/C3INC/ 48 RPI37/CN0/T1CK/RC14 47 SOSCI/C3IND/CN1/RC13 46 RP11/CN49/RD0 45 RP12/PMCS1/CN56/RD11 44 RP3/PMCS2/CN55/RD10 43 RP4/CN54/RD9 42 RP2/RTCC/CN53/RD8 OSC2/CLKO/CN22/RC15 39 OSC1/CLKIN/CN23/RC12 SCL1/CN83/RG2 36 SDA1/CN84/RG3 35 RPI45/SCK1/INT0/CN72/RF6 34 RP30/CN70/RF2 33 RP16/CN71/RF3 © 2008 Microchip Technology Inc. ...
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... MCLR 9 RP27/PMA2/C2INC/CN11/RG9 TMS/RPI33/CN66/RE8 13 TDO/RPI34/CN67/RE9 14 PGEC3/RP18/C1INA/CN7/AN5/RB5 15 PGED3/RP28/C1INB/AN4/CN6/RB4 16 C2INA/AN3/CN5/RB3 17 RP13/C2INB/AN2/CN4/RB2 18 PGEC1/RP1/AN1/CN3/RB1 19 PGED1/RP0/AN0/CN2/RB0 20 Legend: RPn represents remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PIC24FJXXXGA108 Preliminary SOSCO/C3INC/ 60 RPI37/CN0/RC14 59 SOSCI/C3IND/CN1/RC13 58 RP11/CN49/RD0 57 RP12/PMCS1/CN56/RD11 RP3/PMCS2/CN55/RD10 56 RP4/CN54/RD9 55 54 RP2/RTCC/CN53/RD8 53 RPI35/SDA2/CN44/RA15 52 RPI36/SCL2/CN43/RA14 OSC2/CLKO/CN22/RC15 50 ...
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... MCLR 13 RP27/PMA2/C2INC/CN11/RG9 TMS/CN33/RA0 17 RPI33/CN66/RE8 18 RPI34/CN67/RE9 19 PGEC3/RP18/C1INA/AN5/CN7/RB5 20 PGED3/RP28/C1INB/AN4/CN6/RB4 21 C2INA/AN3/CN5/RB3 22 RP13/C2INB/AN2/CN4/RB2 23 PGEC1/RP1/AN1/CN3/RB1 24 PGED1/RP0/AN0/CN2/RB0 25 Legend: RPn represents remappable pins for Peripheral Pin Select feature. DS39905B-page 4 PIC24FJXXXGA110 Preliminary © 2008 Microchip Technology Inc SOSCO/C3INC/ 74 RPI37/CN0/RC14 73 SOSCI/C3IND/CN1/RC13 72 RP11/CN49/RD0 RP12/PMCS1/CN56/RD11 71 RP3/PMCS2/CN55/RD10 70 RP4/CN54/RD9 69 RP2/RTCC/CN53/RD8 68 RPI35/ASDA2/CN44/RA15 67 RPI36/ASCL2/CN43/RA14 OSC2/CLKO/CN22/RC15 64 OSC1/CLKI/CN23/RC12 ...
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... Electrical Characteristics .......................................................................................................................................................... 257 28.0 Packaging Information.............................................................................................................................................................. 271 Appendix A: Revision History............................................................................................................................................................. 281 Index ................................................................................................................................................................................................. 283 The Microchip Web Site ..................................................................................................................................................................... 287 Customer Change Notification Service .............................................................................................................................................. 287 Customer Support .............................................................................................................................................................................. 287 Reader Response .............................................................................................................................................................................. 288 Product Identification System ............................................................................................................................................................ 289 © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39905B-page 6 Preliminary © 2008 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128GA106 • PIC24FJ128GA110 • PIC24FJ192GA106 • PIC24FJ192GA110 • PIC24FJ256GA106 • PIC24FJ256GA110 • PIC24FJ128GA108 • PIC24FJ192GA108 • PIC24FJ256GA108 This family expands on the existing line of Microchip‘s 16-bit general purpose microcontrollers, combining ...
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... This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary features available on the © 2008 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 128GA106 192GA106 DC – 32 MHz 128K 192K 44,032 67,072 16,384 ...
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... Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Preliminary 256GA108 256K 87,552 © 2008 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 128GA110 192GA110 DC – 32 MHz 128K 192K 44,032 67,072 16,384 ...
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... Multiplier (2) MCLR 10-Bit (3) RTCC Timer4/5 ADC SPI UART I2C (3) (3) 1/2/3 1/2/3 1/2/3/4 Preliminary (1) PORTA 16 (13 I/O) PORTB Latch (16 I/ (1) PORTC (8 I/ (1) PORTD (16 I/O) (1) PORTE (10 I/O) (1) PORTF 16-Bit ALU (11 I/O) 16 (1) PORTG (12 I/O) (3) Comparators PMP/PSP CTMU © 2008 Microchip Technology Inc. ...
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... C3INB 54 68 C3INC 48 60 C3IND 47 59 CLKI 39 49 CLKO 40 50 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA ...
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... CN39 — — CN40 — — CN41 — 23 CN42 — 24 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39905B-page 14 Input I/O Buffer TQFP Interrupt-on-Change Inputs Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... CN78 — 74 CN79 — — CN80 — — CN81 — — CN82 — — CN83 37 47 CN84 36 46 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP Interrupt-on-Change Inputs ...
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... I/O ST/TTL 99 I/O ST/TTL 100 I/O ST/TTL 3 I/O ST/TTL 4 I/O ST/TTL 5 I/O ST/TTL 82 O — Parallel Master Port Read Strobe — Parallel Master Port Write Strobe Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... RC3 — 5 RC4 — — RC12 39 49 RC13 47 59 RC14 48 60 RC15 40 50 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 17 I/O ST PORTA Digital I/ I/O ...
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... I/O ST PORTE Digital I/ I/O ST 100 — Reference Clock Output. 87 I/O ST PORTF Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... RP26 5 7 RP27 8 10 RP28 12 16 RP29 30 36 RP30 — 42 RP31 — — Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 90 I/O ST PORTG Digital I/ I/O ...
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... Positive Supply for Microcontroller Core Logic (regulator disabled ANA A/D and Comparator Reference Voltage (low) Input ANA A/D and Comparator Reference Voltage (high) Input. P — Ground Reference for Logic and I/O Pins. 65 Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Control Control Signals to Various Blocks DS39905B-page 22 Data Bus Data Latch PCL Data RAM Address Loop Latch Control Logic 16 RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Preliminary Peripheral Modules © 2008 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39905B-page 24 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. Description Preliminary © 2008 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. ...
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... Instruction Width Preliminary Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ256GA110 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 0157FAh: 44,032 0157FEh 020BFAh: 67,072 020BFEh 02ABFAh: 87,552 02ABFEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2008 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PIC24FJ256GA110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. ...
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... SPI — — — — — — — — — CRC — System NVM/PMD — Preliminary xxA0 xxC0 xxE0 Interrupts — Compare UART I/O — — — — — — — PPS — — — — © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 31 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 32 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 33 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 34 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 35 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 36 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 37 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 38 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 39 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 40 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 41 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 42 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 43 ...
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... PIC24FJ256GA110 FAMILY DS39905B-page 44 Preliminary © 2008 Microchip Technology Inc. ...
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... W15 (before CALL) 000000000 PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits 24 Bits Select 1 0 PSVPAG 8 Bits 23 Bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select © 2008 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PSV Area 800000h Preliminary 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the PSV area. FFFFh This corresponds exactly to the same lower 15 bits of the actual program space address. © 2008 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time. Manual” ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished. Preliminary © 2008 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2008 Microchip Technology Inc. ...
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... W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle Preliminary © 2008 Microchip Technology Inc. ...
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... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
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... SWDTEN bit setting. DS39905B-page 56 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... OST LOCK T — RST T — RST T — RST T — RST T — RST T — RST PWRT Preliminary FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip © 2008 Microchip Technology Inc. ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL ...
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... PIC24FJ256GA110 FAMILY NOTES: DS39905B-page 60 Preliminary © 2008 Microchip Technology Inc. ...
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... PIC24FJ256GA110 family devices non-maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved Preliminary (1) (1) Trap Source © 2008 Microchip Technology Inc. ...
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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h ...
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... Enable Priority IEC0<3> IPC0<14:12> IEC0<7> IPC1<14:12> IEC0<8> IPC2<2:0> IEC1<11> IPC6<14:12> IEC1<12> IPC7<2:0> IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> © 2008 Microchip Technology Inc. ...
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... See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39905B-page 66 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39905B-page 68 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39905B-page 70 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39905B-page 72 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF ...
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... Interrupt request not enabled DS39905B-page 74 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 (1) ...
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... SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 9.4 “Peripheral Pin Select” for more information. DS39905B-page 76 Preliminary © 2008 Microchip Technology Inc. ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...
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... DS39905B-page 78 U-0 U-0 — — U-0 U-0 (1) — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 SI2C2IE — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Unimplemented: Read as ‘0’ DS39905B-page 80 R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE R/W-0 R/W-0 R/W-0 SI2C3IE U3TXIE U3RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U4TXIE U4RXIE bit 8 R/W-0 U-0 U3ERIE — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
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... Unimplemented: Read as ‘0’ DS39905B-page 82 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
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... Interrupt source is disabled DS39905B-page 84 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 88
... Interrupt source is disabled DS39905B-page 86 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 89
... OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...
Page 90
... Interrupt source is disabled DS39905B-page 88 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 92
... Unimplemented: Read as ‘0’ DS39905B-page 90 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 IC6IP2:IC6IP0: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...
Page 94
... Interrupt source is disabled DS39905B-page 92 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 95
... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 ...
Page 96
... Unimplemented: Read as ‘0’ DS39905B-page 94 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 97
... RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 98
... Unimplemented: Read as ‘0’ DS39905B-page 96 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 99
... CTMUIP2:CTMUIP0: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 100
... Unimplemented: Read as ‘0’ DS39905B-page 98 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 SI2C3P2:SI2C3P0: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-0 U4ERIP0 — — R/W-0 ...
Page 102
... DS39905B-page 100 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 OC9IP2:OC9IP0: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 104
... Note that only user interrupts with a priority level less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2008 Microchip Technology Inc. ...
Page 105
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects ...
Page 106
... Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Preliminary the program memory (refer to “Configuration Bits” for further (Configuration Word 2<10:8>), Configuration bits (Configuration FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2008 Microchip Technology Inc. ...
Page 107
... IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY The CLKDIV register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...
Page 108
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. DS39905B-page 106 (2) (3) Preliminary © 2008 Microchip Technology Inc. ...
Page 109
... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 110
... Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 111
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...
Page 112
... R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 RODIV1 RODIV0 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 113
... Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 111 ...
Page 114
... PIC24FJ256GA110 FAMILY NOTES: DS39905B-page 112 Preliminary © 2008 Microchip Technology Inc. ...
Page 115
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “ ...
Page 116
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows fur- possible ther reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. Preliminary © 2008 Microchip Technology Inc. ...
Page 117
... CK WR PORT Data Latch Read LAT Read PORT © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 118
... Make certain that there is no exter- DD nal pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary © 2008 Microchip Technology Inc. ...
Page 119
... RPI32 to RPI45 (or the upper limit for that particular device). See Table 1-4 for a summary of pinout options in each package offering. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 9.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals ...
Page 120
... INT2R5:INT2R0 INT3R5:INT3R0 INT4R5:INT4R0 IC1R5:IC1R0 IC2R5:IC2R0 IC3R5:IC3R0 IC4R5:IC4R0 IC5R5:IC5R0 IC6R5:IC6R0 IC7R5:IC7R0 IC8R5:IC8R0 IC9R5:IC9R0 OCFAR5:OCFAR0 OCFBR5:OCFBR0 SCK1R5:SCK1R0 SDI1R5:SDI1R0 SS1R5:SS1R0 SCK2R5:SCK2R0 SDI2R5:SDI2R0 SS2R5:SS2R0 SCK3R5:SCK3R0 SDI3R5:SDI3R0 SS3R5:SS3R0 T1CKR5:T1CKR0 T2CKR5:T2CKR0 T3CKR5:T3CKR0 T4CKR5:T4CKR0 T5CKR5:T5CKR0 U1CTSR5:U1CTSR0 U1RXR5:U1RXR0 U2CTSR5:U2CTSR0 U2RXR5:U2RXR0 U3CTSR5:U3CTSR0 U3RXR5:U3RXR0 U4CTSR5:U4CTSR0 U4RXR5:U4RXR0 © 2008 Microchip Technology Inc. ...
Page 121
... The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. ® 3: IrDA BCLK functionality uses this output. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY through Register 9-37). The value of the bit field corre- sponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 9-2). ...
Page 122
... IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. RP Pins (I/O) Unimplemented Total RP5, RP15, RP31 2 RP31 11 — 14 Preliminary RPI Pins Unimplemented RPI32-36, RPI38-44 RPI32, RPI39, RPI41 — © 2008 Microchip Technology Inc. ...
Page 123
... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that fea- ture on ...
Page 124
... INT2R3 INT2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT1R1 INT1R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 INT3R1 INT3R0 bit 8 R/W-1 R/W-1 INT2R1 INT2R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 125
... T3CKR5:T3CKR0: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR5:T2CKR0: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 T1CKR4 ...
Page 126
... IC1R3 IC1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 T5CKR1 T5CKR0 bit 8 R/W-1 R/W-1 T4CKR1 T4CKR0 bit Bit is unknown R/W-1 R/W-1 IC2R1 IC2R0 bit 8 R/W-1 R/W-1 IC1R1 IC1R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 127
... IC6R5:IC6R0: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R5:IC5R0: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 IC4R4 ...
Page 128
... OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 IC8R1 IC8R0 bit 8 R/W-1 R/W-1 IC7R1 IC7R0 bit Bit is unknown R/W-1 R/W-1 OCFBR1 OCFBR0 bit 8 R/W-1 R/W-1 OCFAR1 OCFAR0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 129
... Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR5:U3RXR0: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 IC9R4 IC9R3 IC9R2 ...
Page 130
... U2RXR3 U2RXR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 U1CTSR1 U1CTSR0 bit 8 R/W-1 R/W-1 U1RXR1 U1RXR0 bit Bit is unknown R/W-1 R/W-1 U2CTSR1 U2CTSR0 bit 8 R/W-1 R/W-1 U2RXR1 U2RXR0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 131
... U3CTSR5:U3CTSR0: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R5:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 ...
Page 132
... SS2R3 SS2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 SCK2R1 SCK2R0 bit 8 R/W-1 R/W-1 SDI2R1 SDI2R0 bit Bit is unknown R/W-1 R/W-1 SCK3R1 SCK3R0 bit 8 R/W-1 R/W-1 SS2R1 SS2R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 133
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R5:SDI3R0: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 U4CTSR4 U4CTSR3 U4CTSR2 ...
Page 134
... DS39905B-page 132 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS3R4 SS3R3 SS3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 SS3R1 SS3R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 135
... Peripheral output number n is assigned to pin RP3 (see Table 9-2 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R5:RP2R0: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin RP2 (see Table 9-2 for peripheral function numbers). © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP1R4 ...
Page 136
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 (1) (1) (1) RP5R1 RP5R0 bit 8 R/W-0 R/W-0 R/W-0 RP4R1 RP4R0 bit Bit is unknown R/W-0 R/W-0 R/W-0 RP7R1 RP7R0 bit 8 R/W-0 R/W-0 R/W-0 RP6R1 RP6R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 137
... Peripheral output number n is assigned to pin RP11 (see Table 9-2 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R5:RP10R0: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin RP10 (see Table 9-2 for peripheral function numbers). © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 ...
Page 138
... RP14R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 RP13R1 RP13R0 bit 8 R/W-0 R/W-0 RP12R1 RP12R0 bit Bit is unknown R/W-0 R/W-0 (1) (1) (1) RP15R1 RP15R0 bit 8 R/W-0 R/W-0 RP14R1 RP14R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 139
... Peripheral output number n is assigned to pin RP19 (see Table 9-2 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R5:RP18R0: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin RP18 (see Table 9-2 for peripheral function numbers). © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP17R4 ...
Page 140
... RP22R3 RP22R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP21R1 RP21R0 bit 8 R/W-0 R/W-0 RP20R1 RP20R0 bit Bit is unknown R/W-0 R/W-0 RP23R1 RP23R0 bit 8 R/W-0 R/W-0 RP22R1 RP22R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 141
... Peripheral output number n is assigned to pin RP27 (see Table 9-2 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP26R5:RP26R0: RP26 Output Pin Mapping bits Peripheral output number n is assigned to pin RP26 (see Table 9-2 for peripheral function numbers). © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP25R4 ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 RP29R1 RP29R0 bit 8 R/W-0 R/W-0 RP28R1 RP28R0 bit Bit is unknown R/W-0 R/W-0 (1) (1) (1) RP31R1 RP31R0 bit 8 R/W-0 R/W-0 (2) (2) (2) RP30R1 RP30R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 143
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 144
... DS39905B-page 142 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 145
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 146
... The ADC Event Trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. DS39905B-page 144 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) Preliminary TCKPS1:TCKPS0 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync © 2008 Microchip Technology Inc. ...
Page 147
... Equal Note 1: The Timer Clock input must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer3. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 1x Gate Sync 01 ...
Page 148
... DS39905B-page 146 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) Preliminary (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 149
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 3: Changing the value of TMRxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 (1) — ...
Page 150
... PIC24FJ256GA110 FAMILY NOTES: DS39905B-page 148 Preliminary © 2008 Microchip Technology Inc. ...
Page 151
... Reset Trigger and Sync Sources Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 12.1 General Operating Modes 12.1.1 SYNCHRONOUS AND TRIGGER ...
Page 152
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). Preliminary © 2008 Microchip Technology Inc. for both modules configure Trigger ...
Page 153
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 ICTSEL2 ...
Page 154
... DS39905B-page 152 U-0 U-0 — — R/W-0 R/W-0 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary U-0 U-0 R/W-0 — — IC32 bit 8 R/W-0 R/W-0 R/W-0 SYNCSEL1 SYNCSEL0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 155
... Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 156
... OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS Preliminary or synchronization source. If the time base source with the OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 (1) OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt © 2008 Microchip Technology Inc. ...
Page 157
... Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuos pulse events continue indefinitely until terminated. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 13.3 Pulse-Width Modulation (PWM) Mode registers ...
Page 158
... Table 13-1 and Table 13-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively. Preliminary OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt © 2008 Microchip Technology Inc. ...
Page 159
... PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2, Doze mode and PLL are disabled. CY OSC © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY ( F CY log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. ...
Page 160
... R/W-0 R/W-0 OCTSEL2 OCTSEL1 OCTSEL0 R/W-0, HCS R/W-0 R/W-0 OCFLT0 TRIGMODE OCM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (1) (1) OCM1 OCM0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 161
... Output Compare Peripheral x connected to the OCx pin Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 U-0 OCINV — ...
Page 162
... Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. DS39905B-page 160 (1) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) (1) (1) (1) (1) (1) (1) (1) Preliminary © 2008 Microchip Technology Inc. ...
Page 163
... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...
Page 164
... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2008 Microchip Technology Inc. ...
Page 165
... SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
Page 166
... DS39905B-page 164 U-0 U-0 — — SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 167
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 165 ...
Page 168
... R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 169
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — ...
Page 170
... SDIx SDOx Serial Clock SCKx SCKx SSx SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> Preliminary (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (SPIxBUF) © 2008 Microchip Technology Inc. ...
Page 171
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
Page 172
... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2008 Microchip Technology Inc. ...
Page 173
... ASCL2 and ASDA2 during device configuration. Pin assignment is controlled by the I2C2SEL Configu- ration bit; programming this bit (= 0) multiplexes the module to the ASCL2 and ASDA2 pins. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 15.2 Communicating as a Master in a Single Master Environment ...
Page 174
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2008 Microchip Technology Inc. ...
Page 175
... The address bits listed here will never cause an address match, independent of address mask settings. 2: Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 15.4 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “ ...
Page 176
... R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions Slave slave slave) Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 177
... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2 C master. Applicable during master receive master ...
Page 178
... HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared slave) Preliminary R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/ Clearable bit x = Bit is unknown C module is busy © 2008 Microchip Technology Inc. ...
Page 179
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2 C slave device address byte. Preliminary ...
Page 180
... DS39905B-page 178 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 181
... Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
Page 182
... Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) © 2008 Microchip Technology Inc. ...
Page 183
... Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 184
... U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 185
... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 183 ...
Page 186
... R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R-0 R-1 (2) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 187
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 185 ...
Page 188
... PIC24FJ256GA110 FAMILY NOTES: DS39905B-page 186 Preliminary © 2008 Microchip Technology Inc. ...
Page 189
... PMP is highly configurable. FIGURE 17-1: PMP MODULE OVERVIEW PIC24F Parallel Master Port © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Key features of the PMP module include: • Programmable Address Lines • Chip Select Lines • Programmable Strobe Options: - Individual Read and Write Strobes or ...
Page 190
... R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN (1) (1) (1) R/W-0 R/W-0 CS2P CS1P U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary R/W-0 R/W-0 R/W-0 PTWREN PTRDEN bit 8 R/W-0 R/W-0 R/W-0 BEP WRSP RDSP bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 191
... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Preliminary DS39905B-page 189 ...
Page 192
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase multiplexed address phase multiplexed address phase multiplexed address phase Preliminary R/W-0 R/W-0 MODE1 MODE0 bit 8 R/W-0 R/W-0 (1) (1) WAITE1 WAITE0 bit Bit is unknown (1) (2) ) (1) © 2008 Microchip Technology Inc. ...
Page 193
... PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 ADDR<13:8> ...
Page 194
... DS39905B-page 192 U-0 R-0 R-0 — IB3F IB2F U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. R-0 R-0 IB1F IB0F bit 8 R-1 R-1 OB1E OB0E bit Bit is unknown ...
Page 195
... PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set. © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — ...
Page 196
... PMWR PMDOUT1<7:0> (0) PMDOUT2<7:0> (2) PMA<13:0> PMD<7:0> PMCS1 PMCS2 PMRD PMWR Preliminary Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines © 2008 Microchip Technology Inc. ...
Page 197
... MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F FIGURE 17-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMALH PMCS1 PMRD PMWR © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 Address Bus Multiplexed PMALL Data and Address Bus ...
Page 198
... Parallel Peripheral AD<7:0> ALE Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> Preliminary WR Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2008 Microchip Technology Inc. ...
Page 199
... FIGURE 17-12: LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC24F PM<7:0> PMA0 PMRD/PMWR PMCS1 © 2008 Microchip Technology Inc. PIC24FJ256GA110 FAMILY LCD Controller D<7:0> RS R/W E Preliminary Address Bus Data Bus Control Lines DS39905B-page 197 ...
Page 200
... PIC24FJ256GA110 FAMILY NOTES: DS39905B-page 198 Preliminary © 2008 Microchip Technology Inc. ...