PIC24FJ256GA106-I/PT Microchip Technology, PIC24FJ256GA106-I/PT Datasheet - Page 118

• Manufacturer Part Number: PIC24FJ256GA106-I/PT
• Description: IC PIC MCU FLASH 256K 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
9.1.1
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
9.2
The AD1PCFGL and TRIS registers control the opera-
tion of the A/D port pins. Setting a port pin as an analog
input also requires that the corresponding TRIS bit be
set. If the TRIS bit is cleared (output), the digital output
level (V
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
9.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
EXAMPLE 9-1:
DS39905B-page 116
MOV
MOV
NOP
BTSS
OH
0xFF00, W0
W0, TRISBB
PORTB, #13
Configuring Analog Port Pins
or V
OPEN-DRAIN CONFIGURATION
I/O PORT WRITE/READ TIMING
OL
IH
) will be converted.
specification.
PORT WRITE/READ EXAMPLE
DD
(e.g., 5V) on any desired
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
Preliminary
9.3
The input change notification function of the I/O ports
allows the PIC24FJ256GA110 family of devices to gen-
erate interrupt requests to the processor in response to
a change of state on selected input pins. This feature is
capable of detecting input change of states even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, there are up to 81 external
inputs that may be selected (enabled) for generating an
interrupt request on a change of state.
Registers CNEN1 through CNEN6 contain the interrupt
enable control bits for each of the CN input pins. Setting
any of these bits enables a CN interrupt for the corre-
sponding pins.
Each CN pin has a both a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a current
source that is connected to the pin, while the
pull-downs act as a current sink that is connected to the
pin. These eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups and pull-downs are separately enabled
using the CNPU1 through CNPU6 registers (for
pull-ups) and the CNPD1 through CNPD6 registers (for
pull-downs). Each CN pin has individual control bits for
its pull-up and pull-down. Setting a control bit enables
the weak pull-up or pull-down for the corresponding
pin.
When the internal pull-up is selected, the pin pulls up to
V
nal pull-up source when the internal pull-ups are
enabled, as the voltage difference can cause a current
path.
DD
Note:
- 0.7V (typical). Make certain that there is no exter-
Input Change Notification
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
© 2008 Microchip Technology Inc.