PIC24FJ256GA106-I/PT Microchip Technology, PIC24FJ256GA106-I/PT Datasheet - Page 244

• Manufacturer Part Number: PIC24FJ256GA106-I/PT
• Description: IC PIC MCU FLASH 256K 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
The size and type of protection for the segmented code
range are configured by the WPFPx, WPEND, WPCFG
and WPDIS bits in Configuration Word 3. Code seg-
ment protection is enabled by programming the WPDIS
bit (= 0). The WPFP bits specify the size of the segment
to be protected, by specifying the 512-word code page
that is the start or end of the protected segment. The
specified region is inclusive, therefore, this page will
also be protected.
The WPEND bit determines if the protected segment
uses the top or bottom of the program space as a
boundary. Programming WPEND (= 0) sets the bottom
of program memory (000000h) as the lower boundary
of the protected segment. Leaving WPEND unpro-
grammed (= 1) protects the specified page through the
last page of implemented program memory, including
the Configuration Word locations.
A separate bit, WPCFG, is used to independently pro-
tect the last page of program space, including the Flash
Configuration Words. Programming WPCFG (= 0) pro-
tects the last page regardless of the other bit settings.
This may be useful in circumstances where write pro-
tection is needed for both a code segment in the bottom
of memory, as well as the Flash Configuration Words.
The various options for segment code protection are
shown in Table 24-2.
TABLE 24-2:
DS39905B-page 242
WPDIS
Segment Configuration Bits
1
1
0
0
0
0
WPEND
X
X
1
0
1
0
SEGMENT CODE PROTECTION CONFIGURATION OPTIONS
WPCFG
1
0
0
0
1
1
No additional protection enabled; all program memory protection configured by
GCP and GWRP
Last code page protected, including Flash Configuration Words
Addresses from first address of code page defined by WPFP8:WPFP0 through
end of implemented program memory (inclusive) protected, including Flash
Configuration Words
Address 000000h through last address of code page defined by WPFP8:WPFP0
(inclusive) protected
Addresses from first address of code page defined by WPFP8:WPFP0 through
end of implemented program memory (inclusive) protected, including Flash
Configuration Words
Addresses from first address of code page defined by WPFP8:WPFP0 through
end of implemented program memory (inclusive) protected
Preliminary
Write/Erase Protection of Code Segment
24.4.3
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code segment protection setting.
CONFIGURATION REGISTER
PROTECTION
© 2008 Microchip Technology Inc.