PIC18F2610-I/SO Microchip Technology, PIC18F2610-I/SO Datasheet - Page 210
![IC MCU FLASH 32KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2610-I/SO
Manufacturer Part Number
PIC18F2610-I/SO
Description
IC MCU FLASH 32KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18F2515-ISO.pdf
(16 pages)
6.PIC18F2515-ISO.pdf
(6 pages)
7.PIC18F2515-ISO.pdf
(8 pages)
8.PIC18F4510-IPT.pdf
(380 pages)
Specifications of PIC18F2610-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3968 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Height
2.31 mm
Length
17.87 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
7.49 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2610-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- PIC18F2515-ISO PDF datasheet #7
- PIC18F4510-IPT PDF datasheet #8
- Current page: 210 of 380
- Download datasheet (8Mb)
PIC18F2X1X/4X1X
17.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 17-13:
TABLE 17-8:
DS39636A-page 208
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
Note 1:
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
RC7/TX/CK pin
RC7/TX/CK pin
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
RC7/RX/DT
(SCKP = 0)
(SCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
These bits are unimplemented on 28-pin devices and read as ‘0’.
EUSART SYNCHRONOUS
MASTER RECEPTION
Read
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH
ABDOVF
PSPIF
PSPIE
PSPIP
pin
CSRC
SPEN
Q2
Bit 7
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
CREN
SYNC
SCKP
Preliminary
bit 2
TXIE
TXIP
Bit 4
TXIF
bit 3
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
bit 5
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
2004 Microchip Technology Inc.
bit 6
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
bit 7
Bit 0
Q1 Q2 Q3 Q4
Values on
Reset
page
49
52
52
52
51
51
51
51
51
51
‘0’
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