P87C554SBAA,512 NXP Semiconductors, P87C554SBAA,512 Datasheet - Page 49

• Manufacturer Part Number: P87C554SBAA,512
• Description: IC 80C51 MCU 16K OTP 64-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C554SBAA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Cpu Family: 87C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 7-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1254-5; 935263385512; P87C554SBAA

these status codes is detailed in Table 9. The slave transmitter mode
Philips Semiconductors
Table 10.
Slave Transmitter Mode: In the slave transmitter mode, a number
of data bytes are transmitted to a master receiver (see Figure 43).
Data transfer is initialized as in the slave receiver mode. When
S1ADR and S1CON have been initialized, SIO1 waits until it is
addressed by its own slave address followed by the data direction
bit which must be “1” (R) for SIO1 to operate in the slave transmitter
mode. After its own slave address and the R bit have been received,
the serial interrupt flag (SI) is set and a valid status code can be
read from S1STA. This status code is used to vector to an interrupt
service routine, and the appropriate action to be taken for each of
may also be entered if arbitration is lost while SIO1 is in the master
mode (see state B0H).
If the AA bit is reset during a transfer, SIO1 will transmit the last byte
of the transfer and enter state C0H or C8H. SIO1 is switched to the
not addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as
serial data. While AA is reset, SIO1 does not respond to its own
slave address or a general call address. However, the I
monitored, and address recognition may be resumed at any time by
setting AA. This means that the AA bit may be used to temporarily
isolate SIO1 from the I
Miscellaneous States: There are two S1STA codes that do not
correspond to a defined SIO1 hardware state (see Table 10). These
are discussed below.
S1STA = F8H:
This status code indicates that no relevant information is available
because the serial interrupt flag, SI, is not yet set. This occurs
between other states and when SIO1 is not involved in a serial
transfer.
S1STA = 00H:
This status code indicates that a bus error has occurred during an
SIO1 serial transfer. A bus error is caused when a START or STOP
condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error may also be
caused when external interference disturbs the internal SIO1
signals. When a bus error occurs, SI is set. To recover from a bus
error, the STO flag must be set and SI must be cleared. This causes
SIO1 to enter the “not addressed” slave mode (a defined state) and
to clear the STO flag (no other bits in S1CON are affected). The
2002 Mar 25
STATUS
STATUS
(S1STA)
(S1STA)
F8H
00H
CODE
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
capture/compare, high I/O
information available;
No relevant state
SI = 0
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
00H can also occur
when interference
causes SIO1 to enter
an undefined state.
SIO1 HARDWARE
SIO1 HARDWARE
STATUS OF THE
STATUS OF THE
Miscellaneous States
I
2
C BUS AND
2
C bus.
No S1DAT action
No S1DAT action
TO/FROM S1DAT
TO/FROM S1DAT
APPLICATION SOFTWARE RESPONSE
2
C bus is still
STA
0
2
C, PWM,
No S1CON action
TO S1CON
STO
1
47
If the SIO1 hardware detects a repeated START condition on the I
SDA and SCL lines are released (a STOP condition is not
transmitted).
Some Special Cases: The SIO1 hardware has facilities to handle
the following special cases that may occur during a serial transfer:
Simultaneous Repeated START Conditions from Two Masters
A repeated START condition may be generated in the master
transmitter or master receiver modes. A special case occurs if
another master simultaneously generates a repeated START
condition (see Figure 44). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
bus before generating a repeated START condition itself, it will
release the bus, and no interrupt request is generated. If another
master frees the bus by generating a STOP condition, SIO1 will
transmit a normal START condition (state 08H), and a retry of the
total serial data transfer can commence.
D
Arbitration may be lost in the master transmitter and master receiver
modes (see Figure 36). Loss of arbitration is indicated by the
following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 40
and 41).
If the STA flag in S1CON is set by the routines which service these
states, then, if the bus is free again, a START condition (state 08H)
is transmitted without intervention by the CPU, and a retry of the
total serial transfer can commence.
F
In some applications, it may be possible for an uncontrolled source
to cause a bus hang-up. In such situations, the problem may be
caused by interference, temporary interruption of the bus or a
temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks
a STOP condition, then the I
STA flag is set and bus access is not obtained within a reasonable
amount of time, then a forced access to the I
is achieved by setting the STO flag while the STA flag is still set. No
STOP condition is transmitted. The SIO1 hardware behaves as if a
STOP condition was received and is able to transmit a START
condition. The STO flag is cleared by hardware (see Figure 45).
SI
0
ORCED
ATA
T
AA
RANSFER
X
A
CCESS TO THE
Wait or proceed current transfer
Only the internal hardware is affected in the MST or
addressed SLV modes. In all cases, the bus is
released and SIO1 is switched to the not addressed
SLV mode. STO is reset.
A
NEXT ACTION TAKEN BY SIO1 HARDWARE
FTER
L
I
OSS OF
2
C B
2
US
C bus stays busy indefinitely. If the
A
RBITRATION
2
C bus is possible. This
P87C554
Product data
2
C