P87C554SBAA,512 NXP Semiconductors, P87C554SBAA,512 Datasheet - Page 70

• Manufacturer Part Number: P87C554SBAA,512
• Description: IC 80C51 MCU 16K OTP 64-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C554SBAA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Cpu Family: 87C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 7-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1254-5; 935263385512; P87C554SBAA

Philips Semiconductors
2002 Mar 25
WRITE TO SBUF
INSTRUCTION
PORT 0
PORT 2
INPUT DATA
OUTPUT DATA
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
capture/compare, high I/O
CLEAR RI
PSEN
ALE
WR
CLOCK
ALE
t
AVLL
0
t
QVXH
FROM RI OR DPL
A0–A7
t
t
1
XHDV
LLAX
t
AVWL
0
t
t
XLXL
VALID
LLWL
V
CC
0.45V
–0.5
P2.0–P2.7 OR A8–A15 FROM DPH
Figure 51. External Data Memory Write Cycle
t
XHQX
2
Figure 52. External Clock Drive XTAL1
Figure 53. Shift Register Mode Timing
VALID
1
t
QVWX
0.2V
t
CHCL
0.7V
t
CC
XHDX
2
DATA OUT
CC
t
3
C, PWM,
DW
t
WLWH
–0.1
VALID
2
68
t
CLCX
4
t
CLCL
VALID
3
t
CHCX
t
CLCH
t
WHLH
t
5
WHQX
SU00009
VALID
4
A0–A7 FROM PCL
A8–A15 FROM PCH
6
VALID
5
7
VALID
6
P87C554
INSTR IN
Product data
8
VALID
SU00213
SET TI
SET RI
SU00027
7