Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 367

IC ZNEO MCU FLASH 128K 100LQFP

Z16F2811AL20SG

Manufacturer Part Number
Z16F2811AL20SG
Description
IC ZNEO MCU FLASH 128K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheets

Specifications of Z16F2811AL20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4533

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Table 194. SPI Master Mode Timing
PS022008-0810
Parameter
SPI Master
T
T
T
1
2
3
(Output)
(Input)
MOSI
MISO
SCK
SPI Master Mode Timing
Figure 76
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
Abbreviation
SCK Rise to MOSI output Valid Delay
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
T1
and
Table 194
Figure 76. SPI Master Mode Timing
provides timing information for SPI Master mode pins. Timing is
P R E L I M I N A R Y
T2
Input Data
T3
Output Data
Min
–5
20
0
Delay (ns)
Product Specification
Electrical Characteristics
ZNEO
Max
+5
Z16F Series
351

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