C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 128

• Manufacturer Part Number: C8051F040-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 13-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 64
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Data Rom Size: 64 KB
• A/d Bit Size: 12 bit
• A/d Channels Available: 13
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1204

C8051F040/1/2/3/4/5/6/7
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support logic. The re-programmable Flash can also be read and
changed a single byte at a time by the application software using the MOVC and MOVX instructions. This
feature allows program memory to be used for non-volatile data storage as well as updating program code
under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including
interrupt service routines), examination of the program's call stack, and reading/writing the contents of reg-
isters and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring
no RAM, Stack, timers, or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via its JTAG interface to provide
fast and efficient in-system device programming and debugging. Third party macro assemblers and C
compilers are also available.
128
Number of Instructions
Clocks to Execute
26
1
50
2
2/3
Rev. 1.5
5
14
3
3/4
7
4
3
4/5
1
5
2
8
1